Z8F021ASH020SC datasheet(53/276 Pages) ZILOG

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PS022815-0206

General-Purpose I/O

Z8 Encore! XP® 4K Series

Product Specification

PA0 and PA6 contain two different timer functions, a timer input and a complementary

timer output. Both of these functions require the same GPIO configuration, the selection

between the two is based on the timer mode. See Timers on page 62 for more details.

Direct LED Drive

The Port C pins provide a current sinked output capable of driving an LED without requir-

ing an external resistor. The output sinks current at programmable levels of 3 mA, 7 mA,

13 mA and 20 mA. This mode is enabled through the Alternate Function sub-register

AFS1 and is programmable through the LED control registers. The LED Drive Enable

(LEDEN) register turns on the drivers. The LED Drive Level (LEDLVLH and LEDLVLL)

registers select the sink current.

For correct function, the LED anode must be connected to VDD and the cathode to the

GPIO pin.

Using all Port C pins in LED drive mode with maximum current may result in excessive

total current. Refer to the Electrical Characteristics on page 212 for the maximum total

current for the applicable package.

Shared Reset Pin

On the 20 and 28-pin devices, the Port D0 pin shares function with a bi-directional reset

pin. Unlike all other I/O pins, this pin does not default to GPIO function on power-up.

This pin acts as a bi-directional reset until user software re-configures it. The Port D0 pin

is output-only when in GPIO mode.

On the 8-pin product versions, the reset pin is shared with PortA2, but the pin is not lim-

ited to output-only when in GPIO mode.

If PA2 on the 8-pin product is reconfigured as an input, take care that no external stim-

ulus drives the pin low during any reset sequence. Since PA2 returns to its RESET al-

ternate function during system resets, driving it low will hold the chip in a reset state

until the pin is released. The same applies to the PDO pin on the 28-pin product.

Shared Debug Pin

On the 8-pin version of this device only, the Debug pin shares function with the PortA0

GPIO pin. This pin performs as a general purpose input pin on power-up, but the debug

logic monitors this pin during the reset sequence to determine if the unlock sequence

occurs. If the unlock sequence is present, the debug function is unlocked and the pin no

longer functions as a GPIO pin. If it is not present, the debug feature is disabled until/

unless another reset event occurs. For more details, see On-Chip Debugger on page 167

Caution:

Z8F021ASH020SC Datasheet(PDF) 53 Page - Zilog, Inc.