Z8F021ASH020SC datasheet(46/276 Pages) ZILOG

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PS022815-0206

Reset, STOP Mode Recovery and Low Voltage Detection

Z8 Encore! XP® 4K Series

Product Specification

STOP Mode Recovery Using the External RESET Pin

When the Z8 Encore! XP® 4K Series device is in STOP Mode and the external RESET pin

is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET

pin, the Low pulse must be greater than the minimum width specified, or it is ignored. See

Electrical Characteristics on page 212 for details.

Low Voltage Detection

In addition to the Voltage Brown-out Reset (VBO) described above, it is also possible to

generate an interrupt when the supply voltage drops below a user-selected value. See Trim

Bit Address 0003H on page 154. for details about the Low Voltage Detection (LVD)

threshold levels available. The LVD function is available on the 8-pin product versions

only.

When the supply voltage drops below the LVD threshold, the LVD bit of the Reset Status

(RSTSTAT) register is set to one. This bit remains one until the low-voltage condition

goes away. Reading or writing this bit does not clear it. The LVD circuit can also generate

an interrupt when so enabled. (See Interrupt Vectors and Priority on page 53.) The LVD bit

is NOT latched, so enabling the interrupt is the only way to guarantee detection of a tran-

sient low voltage event.

The LVD functionality depends on circuitry shared with the VBO block; therefore dis-

abling the VBO also disables the LVD.

Reset Register Definitions

Reset Status Register

The Reset Status (RSTSTAT) register is a read-only register that indicates the source of

the most recent Reset event, indicates a STOP Mode Recovery event, and indicates a

Watch-Dog Timer time-out. Reading this register resets the upper four bits to 0.

This register shares its address with the Watch-Dog Timer control register, which is write-

only (Table 12).

Z8F021ASH020SC Datasheet(PDF) 46 Page - Zilog, Inc.