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Z8F021ASH020SC Datasheet(PDF) 17 Page - Zilog, Inc. |
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Z8F021ASH020SC Datasheet(HTML) 17 Page - Zilog, Inc. |
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17 / 276 page ![]() PS022815-0206 List of Tables Z8 Encore! XP® 4K Series Product Specification xvii Table 58. Watch-Dog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . 86 Table 59. Watch-Dog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . 87 Table 60. Watch-Dog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . 87 Table 61. Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . 88 Table 62. UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . 100 Table 63. UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . 101 Table 64. UART Status 0 Register (U0STAT0) . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 65. UART Status 1 Register (U0STAT1) . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 66. UART Control 0 Register (U0CTL0). . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 67. UART Control 1 Register (U0CTL1). . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 68. UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . 106 Table 69. UART Baud Rate High Byte Register (U0BRH) . . . . . . . . . . . . . . . . 106 Table 70. UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . 106 Table 71. UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 72. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 73. ADC Control/Status Register 1 (ADCCTL1). . . . . . . . . . . . . . . . . . . 126 Table 74. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . 127 Table 75. ADC Data Low Bits Register (ADCD_L). . . . . . . . . . . . . . . . . . . . . . 127 Table 76. ADC High Threshold High Byte (ADCTHH) . . . . . . . . . . . . . . . . . . . 128 Table 77. ADC Low Threshold High Byte (ADCTLH). . . . . . . . . . . . . . . . . . . . 128 Table 78. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . 131 Table 79. Z8 Encore! XP“ 4K Series Flash Memory Configurations . . . . . . . . 136 Table 80. Flash Code Protection Using the Flash Option Bits . . . . . . . . . . . . . 141 Table 81. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 82. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 83. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 84. Flash Sector Protect Register (FPROT). . . . . . . . . . . . . . . . . . . . . . 146 Table 85. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . 147 Table 86. Flash Frequency Low Byte Register (FFREQL). . . . . . . . . . . . . . . . 147 Table 87. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . 150 |
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