Z8F021ASH020SC datasheet(41/276 Pages) ZILOG

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PS022815-0206

Reset, STOP Mode Recovery and Low Voltage Detection

Z8 Encore! XP® 4K Series

Product Specification

Reset Sources

Table 10 lists the possible sources of a system reset.

Power-On Reset

Z8 Encore! XP® 4K Series devices contain an internal power-on reset (POR) circuit. The

POR circuit monitors the supply voltage and holds the device in the Reset state until the

supply voltage reaches a safe operating level. After the supply voltage exceeds the POR

voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has

timed out. If the crystal oscillator is enabled by the option bits, this timeout is longer.

After the Z8 Encore! XP® 4K Series device exits the Power-On Reset state, the eZ8 CPU

fetches the Reset vector. Following Power-On Reset, the POR status bit in the Watch-Dog

Timer Control (WDTCTL) register is set to 1.

Figure 5 illustrates Power-On Reset operation. Refer to the Electrical Characteristics on

page 212 for the POR threshold voltage (VPOR).

Table 10. Reset Sources and Resulting Reset Type

Operating Mode

Reset Source

Special Conditions

NORMAL or HALT

modes

Power-On Reset / Voltage Brown-

Out

Reset delay begins after supply voltage

exceeds POR level

Watch-Dog Timer time-out

when configured for Reset

None

RESET pin assertion

All reset pulses less than three system clocks

in width are ignored.

On-Chip Debugger initiated Reset

(OCDCTL[0] set to 1)

System Reset, except the On-Chip Debugger

is unaffected by the reset

STOP mode

Power-On Reset / Voltage Brown-

Out

Reset delay begins after supply voltage

exceeds POR level

RESET pin assertion

All reset pulses less than the specified analog

delay are ignored. See

Table 134 on page 219

DBG pin driven Low

None

Z8F021ASH020SC Datasheet(PDF) 41 Page - Zilog, Inc.

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