DFE252012F-R47M datasheet(59/122 Pages) AD

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protocols:

● Writing to a single register

● Writing to multiple sequential registers with an automatically incrementing data pointer

● Reading from a single register

● Reading from multiple sequential registers with an automatically increased data pointer

For additional information about the I2C protocols, refer to the I2C specification.

HS Extension Mode

The MAX77542 supports a special I2C feature called HS extension mode. The HS extension feature keeps the high-

speed operation even after a stop condition. This eliminates the need for a HS master code issued by an I2C master

controller when the I2C master controller wants to stay in the HS mode for multiple read/write cycles.

As shown in Figure 14, the HS extension mode can be enabled by setting the HS_EXT_EN bit while the I2C bus operates

in the LS (standard, fast, or fast-mode plus) mode only.

LS MODE

(HS_EXT_EN = 0)

LS MODE

(HS_EXT_EN = 1)

HS MODE

(HS_EXT_EN = 0)

HS MODE

(HS_EXT_EN = 1)

HS MASTER CODE

STOP CONDITION

HS MASTER CODE

SET HS_EXT_EN = 1

SET HS_EXT_EN = 0

Figure 14. I2C Operating Mode State Diagram

I2C Watchdog Timer

The MAX77542 contains an I2C watchdog timer to ensure reliable operation of the I2C bus. The I2C watchdog timer

helps the system recover from I2C bus hang-ups that can occur when devices on the I2C bus operate out of sync from

each other due to noise or poor system design. In most cases, the bus master can clear the I2C bus hang-ups by issuing

nine consecutive STOP commands. However, to account for unforeseen system issues, the I2C watchdog timer serves

as a backup protection method for recovering from the I2C bus hang-ups.

The MAX77542 supports four timer options (31ms, 62ms, 124ms, and 248ms) controlled by the WD_TMR[1:0] bit. The

I2C watchdog timer is enabled when WD_EN bit is set to 1. While the I2C watchdog timer is enabled, the MAX77542

monitors the time between a start and a stop condition and resets the I2C state machine if this time ever exceeds the

selected timer option.

The I2C watchdog timer is disabled by default. With the I2C watchdog timer disabled, the device meets the 0Hz SCL

frequency requirements in the I2C specification. Activating the I2C watchdog timer defeats the 0Hz specification and this

0Hz capability is not needed in many cases.

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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