DFE252012F-R47M datasheet(47/122 Pages) AD

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buck controller forces refresh pulses 16 times with an interval of 3μs.

Frequency Tracking (FTRAK)

The MAX77542 supports the frequency tracking feature. When a valid external clock is detected on the MFIOx input

(when CLKDET_Mx function is selected), the corresponding buck converter enters FPWM mode regardless of its

operating mode setting and tracks the external frequency by modulating on-times. This event triggers the MFIOx_I

interrupt if unmasked. When the external tracking feature is enabled, Buck1 and Buck3 attempt to track the beginning of

on-times to the rising edges of the external clock, while Buck2 and Buck4 attempt to track the beginning of on-times to

the falling edges of the external clock.

Table 12. Mx_FTRAK Enable Truth Table

CLKDET_Mx

(MFIOx)

Mx_FTRAK

PLL

BUCK OPERATING MODE

NOTE

Not Detected

Disabled

Depends on Buck Mode Setting

No Tracking

Not Detected

Enabled

Depends on Buck Mode Setting

Internal Frequency Tracking

Detected

Enabled

FPWM

External Frequency Tracking

Detected

Enabled

FPWM

External Frequency Tracking

As shown in Table 12, the bucks can also track an internal clock. When the FTRAK function is enabled (Mx_FTRAK =

1), the corresponding buck tracks the internal PLL frequency (set by the Mx_FREQ[1:0] bits) if no valid external clock is

applied. In case a valid external clock is detected while the corresponding buck is tracking the internal PLL, it switches

to the external clock tracking. The frequency window for both external and internal tracking is about ±5% of the nominal

switching frequency. The frequency tracking operation is vaild whenever one of the buck converters is enabled. The

CLKDET_Mx (MFIOx) must be driven either low or high to prevent chattering or false tracking (see Figure 7).

PLL FSW

STABILIZER

CLKDET_Mx

(NOTE 1)

INTERNAL

OSC

EXTERNAL

CLK DETECT

TON

GENERATOR

MFIOx_I

NOTE 1: MFIOx IS ASSIGNED FOR THE EXTERNAL CLOCK DETECTION FUNCTION.

Figure 7. Frequency Tracking

The phase sequences with the internal and the external frequency tracking are shown in Table 13.

Table 13. Phase Sequence

PHASE CONFIGURATION

INTERNAL FTRAK

EXTERNAL FTRAK

1+1+1+1

PH1(M): 0

⁰

PH2(M): 180

⁰

PH3(M): 90

⁰

PH4(M): 270

⁰

PH1(M): Rising Edge

PH2(M): Falling Edge

PH3(M): Rising Edge

PH4(M): Falling Edge

2+1+1

PH1(M): 0

⁰

PH2(S): 180

⁰

PH3(M): 90

⁰

PH4(M): 270

⁰

PH1(M): Rising Edge

PH2(S): 180

⁰ from M1

PH3(M): Rising Edge

PH4(M): Falling Edge

2+2

PH1(M): 0

⁰

PH2(S): 180

⁰

PH3(M): 90

⁰

PH4(S): 270

⁰

PH1(M): Rising Edge

PH2(S): 180

⁰ from M1

PH3(M): Rising Edge

PH4(S): 180

⁰ from M3

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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DFE252012F-R47M Datasheet(PDF) 47 Page - Analog Devices

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