DFE252012F-R47M datasheet(49/122 Pages) AD

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LFSR VALUE

LFSR CLOCK PERIOD (1/FLFSR)

FLFSR = FSS_MOD × [2N - 1].

N = LFSR WIDTH (4 BITS).

FSS_MOD = MODULATION RATE (1, 3, 5, OR 7kHz).

ΔFSS = MODULATION ENVELOPE (±8%, ±12%, OR ±16%).

FSW(NOM)

FSW(NOM) + ΔFSS

FSW(NOM) - ΔFSS

REPEAT PERIOD (1/FSS_MOD)

FSW

Figure 9. 4-Bit Pseudo-Random Modulation Signal Example

Triangular Pattern

The triangular engine uses a 4-bit up/down synchronous counter to create a stepped triangle pattern as shown in Figure

10. The counter value is converted to an analog signal and then amplified before being added to the output of the on-time

generator circuit. The counter value progressively shortens and lengthens the on-time. This causes the buck controller

to progressively increase and decrease the switching frequency to maintain voltage regulation. Each buck has its own

triangular pattern generator.

CLOCK

UP/DOWN

COUNTER

GAIN

DAC

REF

TRIANGULAR

MODULATION SIGNAL

Mx_SSM_PAT[1:0]

DECODE

ENVELOPE

RATE

Mx_SS_ENV[1:0]

Mx_SS_FREQ[1:0]

Figure 10. Triangular Modulator Engine

The modulation envelope and frequency are programmable with the Mx_SS_ENV[1:0] and the Mx_FREQ[1:0] bits. The

FSS_MOD sets the frequency at which the counter returns to the same value. The clock rate of the counter is the FCOUNT.

This is the frequency at which the frequency changes from one value to another. An example is shown in Figure 11.

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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DFE252012F-R47M Datasheet(PDF) 49 Page - Analog Devices