DFE252012F-R47M datasheet(56/122 Pages) AD

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ADC Mux Input (ADCMUX)

When the MFIO8 is configured as an ADC mux input, the MAX77542 can covert the voltage applied to this input. The

effective input-voltage range is from 0V to 1.195V and the readback data will be available at the ADC_DATA11[7:0]

ADC mux must not exceed the VDD (1.9V typ).

Debounce Timer

When the MFIOx are configured as logic inputs, a debounce timer is set by the MFIOx_DEB[2:0] bits to avoid logic signal

chattering due to input-signal glitches or bouncing. The timer-setting options are shown in Table 16.

When the system clock is disabled (all the buck outputs are in an off state and the ADC is disabled), there is an

additional debounce time (< 5μs) in addition to the selected debounce timer value (except for the no-debounce option).

The additional debounce time is avoided when the CLK_EN bit is set to 1 through the I2C interface, allowing the system

clock to be enabled even in standby state at a cost of 35μA (typ) additional quiescent current.

Table 16. Debounce Timer Setting

MFIOx_DEB[2:0]

TIMER SETTING

0x0

No Debounce

0x1

0.55μs

0x2

1μs

0x3

2μs

0x4

4μs

0x5

8μs

0x6

16μs

0x7

32μs

Internal Pull-Down and Pull-Up Resistor

When the MFIOx are configured as logic inputs, an internal pull-down or pull-up resistance is selected by the

MFIOx_PDPU[1:0] bits as shown in Table 17. For the system reset input function (MFIOx_FUNC[3:0] = 0xA), the

corresponding MFIOx pin is pulled up to the VIO pin with an internal 100kΩ resistor regardless of the MFIOx_PDPU[1:0]

bits.

Table 17. Internal Resistor Setting

MFIOx_PDPU[1:0]

RESISTOR SETTING

0x0

800kΩ Pull-Down to AGND

0x1

100kΩ Pull-Down to AGND

0x2

100kΩ Pull-Up to VIO

0x3

Disable (No Pull-Down or Pull-Up)

Output Driver Mode

When the MFIOx are configured as POK, FPSO, or GPO function, either an open-drain or a push-pull output mode can

be selected by MFIOx_DRV_MODE bits. In push-pull mode, the maximum driving current is limited to 2mA.

Detailed Description—ADC

The MAX77542 has an 8-bit successive approximation register (SAR) ADC with eleven multiplexers for supporting the

telemetry feature (see Figure 13). The eleven multiplexers are assigned for the output current and the output voltage

of each buck converter, the VSYS voltage, the junction temperature, and an external input through a MFIO. Each ADC

channel is individually controlled through the I2C interface and has a set of interrupt and interrupt mask bits. When

unmasked, the interrupt bit sets whenever the ADC data is ready to be read.

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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