DFE252012F-R47M datasheet(35/122 Pages) AD

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Table 3. Device Configuration by RCFG2 (continued)

RCFG2 (Ω)

M1_ILIM (A)

M2_ILIM (A)

M3_ILIM (A)

M4_ILIM (A)

Mx_FREQ (MHz)

30.9k

3.5

5.5

3.5

1.0

36.5k

3.5

5.5

3.5

1.5

42.2k

3.5

5.5

1.0

48.7k

3.5

5.5

1.5

56.2k

3.5

5.5

3.5

1.0

64.9k

3.5

5.5

3.5

1.5

75.0k

3.5

5.5

1.0

86.6k

3.5

5.5

1.5

100k

3.5

1.0

≥ 115k

Factory Option

Output Enable Control

The MAX77542 has eight multifunction I/Os that can be selected for output enable inputs. When the MFIOx is pulled

above the VIH (EN_Mx function is selected), the corresponding buck output is enabled. The buck outputs can also be

turned on by setting the Mx_EN bits to 1 through I2C. The logical interaction between the EN_Mx (MFIOx) pins and their

corresponding I2C enable bits (Mx_EN) is OR. For example, the Master1 is enabled when the M1_EN bit or the EN_M1

(MFIOx) signal is set to 1. When all active signals are 0, the corresponding master phase is turned off. The serial interface

is active whenever the VDD regulator is enabled (see Table 1).

Flexible Power Sequencer (FPS)

The MAX77542 supports a flexible power sequencer that controls programmable startup and shutdown delay times of

each master phase. A startup or a shutdown sequence is initiated by either the FPS_EN bit or global output enable

function (FPSI) of the MFIOx. The startup and shutdown delay times between are individually programmable from 0ms to

56ms (15 slots with 0.5ms/1ms/2ms/4ms of step size) with a no-startup option. The startup delay times are programmable

by the Mx_STUP_DLY[3:0] and the FPSO_STUP_DLY[3:0] bits and their default values are set by OTPs, while the

shutdown delay times are programmable by the Mx_SHDN_DLY[3:0] and the FPSO_SHDN_DLY[3:0] bits only. The

delay time steps and the delay times for all master phases are programmable. When the no-startup option is selected,

the corresponding buck is excluded from the FPS resources.

Once a startup or a shutdown sequence is initiated, the FPS_EN bit or the FPSI input is ignored (deactivated) until

the sequence is completed. During startup and shutdown sequences, any changes in the Mx_STUP_DLY[3:0], the

Mx_SHDN_DLY[3:0], and the DLY_STEP[1:0] bits are also not effective until the sequence ends.

If any master phases are turned on by the Mx_EN bits or the enable function (EN_Mx) of the MFIOx before initiating

a startup or a shutdown sequence, the startup or the shutdown sequence does not affect the master phase(s) already

turned on individually. A typical startup and shutdown sequence are shown in Figure 2.

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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