DFE252012F-R47M datasheet(54/122 Pages) AD

54 / 122 page

Table 15. MFIO I/O Selection (continued)

0x5

N/A

Low

High

0x6

N/A

Low

0x7

N/A

Low

High Impedance

*MFIOx_SEL[2:0] bits are redundant to FPSI, FPSO, RSTINB, RSTOB, TWARNB, GPI, and ADCMUX functions.

Output Enable (EN)

When the MFIOx are configured as output enable pins, the enable logic of a buck converter is an OR logic of the

MFIOx and the corresponding enable register bit (Mx_EN). For example, if the MFIO1 is assigned to Buck Master1

enable (MFIO1_FUNC[3:0] = 0x0 and MFIO1_SEL[2:0] = 0x0), Buck Master1 enable is controlled by the MFIO1 pin

and the M1_EN bit. In case more than one MFIO is configured as the same enable function (e.g., MFIO2_FUNC[3:0] =

MFIO3_FUNC[3:0] = 0x0 and MFIO2_SEL[2:0] = MFIO3_SEL[2:0] = 0x1), those inputs are OR’ed with the M2_EN bit.

Low-Power Mode (LPM)

When the MFIOx are configured as low-power mode pins, the low-power mode logic of a specific buck converter is an

OR logic of the MFIOx and the corresponding enable register bit (Mx_LPM). See the Low-Power Skip (LP-SKIP) Mode

section for more information.

FPWM Mode (FPWM)

When the MFIOx are configured as the FPWM control input, the FPWM control logic of a specific buck converter is an OR

logic of the MFIOx and the corresponding enable register bit (Mx_FPWM). See the Forced-PWM (FPWM) Mode section

for more information.

External Clock Detection (CLKDET)

When the MFIOx are configured as external clock detection inputs, the corresponding buck converter tracks a valid

external clock signal at the MFIOx input. When a valid external clock is detected, the MFIOx status bit sets to 1 which

initiates a corresponding interrupt bit when unmasked. The external frequency detection is deactivated when all buck

outputs are disabled. Note that no more than one MFIO must be assigned as an external clock detection function for a

specific buck converter at a time. See the Frequency Tracking (FTRAK) section for more information.

Clock Output (CLKOUT)

The MFIOx is configured as a clock output (active-high, push-pull) when MFIOx_FUNC[3:0] = 0x4. The CLKOUT provides

the same frequency as the nominal switching frequency of the Buck Master1 which is selected by the M1_FREQ[1:0] bits.

For supporting a phase interleaving feature between multiple devices, the CLKOUT signal can be shifted by 0 to 3 clocks

from the Buck Master1 frequency with the MFIOx_SEL[2:0] bits. The CLKOUT is disabled when all the buck outputs are

turned off. In case the CLKOUT is required in the system even when all the buck outputs are disabled, the CLK_EN bit

(0x0C) needs to be set to 1.

Output-Voltage Selection (VSEL)

When the MFIOx are configured as voltage-selection pins, the output voltage of a specific buck converter is set by

the Mx_VOUT_H[7:0] and Mx_VOUT_L[7:0] registers based on the VSEL_Mx input. For example, if MFIO1_FUNC[3:0]

= 0x5 and MFIO1_SEL[2:0] = 0x0, the output voltage of Buck Master1 is set by the M1_VOUT_H[7:0] and the

M1_VOUT_L[7:0] when MFIO1 = high and MFIO1 = low, respectively. In case more than one MFIO isconfigured as the

same voltage-selection function, those inputs are OR’ed. During the output-voltage transition, the ramp-up/ramp-down

slew rate is controlled by the Mx_RU_SR[2:0] and the Mx_RD_SR[2:0].

Boot (Default) Output-Voltage Selection (VB)

When the MFIOx are configured as boot (default) voltage-selection pins, the output voltage of a specific buck converter

is set by the Mx_VOUT_H[7:0] (or the Mx_VOUT_L[7:0]) and Mx_VOUT_B[7:0] registers based on the input logic.

For example, if MFIO1_FUNC[3:0] = 0x6 and MFIO1_SEL[2:0] = 0x1, the output voltage of Buck Master2 is set by

the M2_VOUT_H[7:0] (or the M2_VOUT_L[7:0]) and the M2_VOUT_B[7:0] when MFIO1 = high and MFIO1 = low,

respectively. In case more than one MFIO is configured as the same voltage-selection function, the VB is an AND logic of

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

www.analog.com

Analog Devices | 54

DFE252012F-R47M Datasheet(PDF) 54 Page - Analog Devices

DFE252012F-R47M Datasheet(HTML) 54 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL