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those inputs. During the output-voltage transition, the ramp-up/ramp-down slew rate is controlled by the Mx_RU_SR[2:0]

and the Mx_RD_SR[2:0].

Power-OK (POK) Output

The MFIOx can be configured as a power-OK (POK) output of a specific buck converter. For example, if the MFIO1 is

assigned to Buck Master1 POK output (MFIO1_FUNC[3:0] = 0x7 and MFIO1_SEL[2:0] = 0x0), the MFIO1 pin goes high

if Buck Master1 output voltage rises above the VPOK_R (typ 82% of the VOUT target) when soft-start is completed. In

case Buck Master1 output falls below the VPOK_F (typ 78% of the VOUT target), the MFIO1 goes low. When the MFIOx

is configured as an open-drain POK output, an external pull-up resistor (typ 10kΩ to 100kΩ) is required.

FPS Input (FPSI)

When a MFIOx is configured as an FPS enable input, the enable logic of the flexible power sequencer is an OR logic

of the MFIOx and the FPS_EN bit. When either signal becomes logic high, the MAX77542 initiates a startup sequence

which is determined by the GLB_CFG1 through GLB_CFG6 registers. If both signals become logic low, it triggers a

shutdown sequence.

FPS Output (FPSO)

When a MFIOx is configured as an FPS output pin, the MFIOx pin can drive the enable signals of other devices. As

a part of the startup and shutdown sequence, the MFIOx goes high or low based on the FPSO_STUP_DLY[3:0], the

FPSO_SHDN_DLY[3:0], and the DLY_STEP[1:0] bits. When the MFIOx is configured as an open-drain FPS output, an

external pull-up resistor (typ 10kΩ to 100kΩ) is required.

System Reset Input (RSTINB)

When a MFIOx is configured as a system reset input pin, a logic-low signal (active-low, pulled up to the VIO pin with

an internal 100kΩ resistor) longer than its debounce timer setting is considered as a valid reset input signal. If the

RSTINB_SHDN bit is set to 1, a valid reset input signal initiates a reset of all functional registers (both Type O and Type

F) to their POR default values for 1μs. When the RSTINB_SHDN bit is set to 0, the MAX77542 ignores the RSTINB input

and takes no action. In case more than one MFIO is configured as the system reset input function, the RSTINB is an

AND logic of those inputs.

System Reset Output (RSTOB)

When a MFIOx is configured as a system reset output pin, the MAX77542 generates a reset output signal (active-low,

open drain) to indicate a fault condition of the device to a host processor or companion devices. The Mx_RSTOB_EN,

the TSHDN_RSTOB_EN, and the UVLO_RSTOB_EN bits allow the host processor to configure which fault condition

triggers the reset output signal. Note that a short-circuit protection (SCP) event asserts the system reset signal for about

3μs and de-asserts it as the SCP event turns off the corresponding buck output.

Thermal Warning Output (TWARNB)

When a MFIOx is configured as a thermal warning output pin, the MAX77542 generates a logic signal (active-low, open

drain) to indicate that the junction temperature of the die reaches the thermal warning threshold. The TWARN_TH[2:0]

bits allow a host processor to set the thermal warning threshold between +95ºC and +130ºC with 5ºC steps.

General-Purpose Input (GPI)

The MFIOx pins are configured as general-purpose inputs when MFIOx_FUNC[3:0] = 0xD. In GPI mode, the

corresponding status bits (MFIOx) represent the current logic data at the MFIOx inputs. When unmasked, toggling of

input logic generates an interrupt. The debounce timer and the internal pull-down resistor settings are configured by the

MFIOx_DEB[2:0] and the MFIOx_PDPU[1:0] bits.

General-Purpose Output (GPO)

The MFIOx pins are configured as general-purpose outputs when MFIOx_FUNC[3:0] = 0xE. In GPO mode, the

MFIOx_SEL[2:0] determines the output data either logic high, logic low, or high impedance (see Table 15). When the

MFIOx is configured as an open-drain GPO, an external pull-up resistor (typ 10kΩ to 100kΩ) is required.

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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