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THERMAL WARNING

(TWARN = 1)

NO THERMAL WARNING

(TWARN = TSHDN = 0)

THERMAL SHUTDOWN

(TWARN = TSHDN = 1)

DISABLE ALL OUTPUTS

IMMEDIATELY

TJ ≥ +165°C

TJ ≤ +150°C

TJ ≥ TWARN_TH[2:0]

THERMAL MONITOR DISABLED

ONE OF OUTPUTS ENABLED

OR FTMON_EN = 1

ALL OUTPUTS DISABLED

AND

AND FTMON_EN = 0

TJ ≤ (TWARN_TH[2:0] - 15°C)

Figure 3. Thermal Warning and Thermal Shutdown

Reset Input and Output

All functional registers (both Type O and Type F) of the MAX77542 can be reset to their POR default values when a valid

reset signal is detected at one of the MFIOx pins. To activate this feature, one of the MFIOx pins must be configured as

system reset input (active-low) function (MFIOx_FUNC[3:0] = 0xA) and the RSTINB_SHDN needs to be set to 1. To avoid

a false trigger by glitches, it is recommended to have a proper debounce timer on this input by setting the corresponding

MFIOx_DEB[2:0] bit. See the System Reset Input (RSTINB) for more details.

The MAX77542 also features "System Reset Output" by configuring one of the MFIOx pins (MFIOx_FUNC[3:0] =

0xB). "System Reset Output" is an active-low open drain and it asserts when one of fault events (which are linked

to the reset output) occurs. To link "System Reset Output" to specific fault considerations, the Mx_RSTOB_EN, the

TSHDN_RSTOB_EN, and/or the UVLO_RSTOB_EN bits need to be set to 1. As soon as the fault condition that caused

the reset output to assert is cleared, the reset output signal will be de-asserted. See the System Reset Output (RSTOB)

section for more details.

Interrupt (IRQB), Mask and Status

The IRQB is an active-low, open-drain output that indicates to a host processor that the status on the MAX77542 has

changed. The IRQB is the logical "NOR" of all unmasked interrupt bits. See the Register Map section for a full list of

available status and interrupt bits.

The IRQB output asserts (goes low) anytime an unmasked interrupt bit is triggered. The host processor reads the

interrupt source register (0x00) and the interrupt registers that are indicated by the interrupt source register to check the

cause of the interrupt event. Note that the interrupt source register is cleared when the corresponding interrupt register

group is read by the host processor. All the interrupt events are edge-triggered. Therefore, the same interrupt is not

generated repeatedly even though the interrupt condition persists.

Each interrupt register can be read at a time and all interrupt bits are clear-on-read bits. The IRQB output de-asserts

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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