DFE252012F-R47M datasheet(46/122 Pages) AD

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setting due to limited sourcing and the sinking current capabilities of bucks under given circuit parameters and operating

conditions. See Table 10 for more information.

Dynamic Output-Voltage Scaling

In a typical processing power application, there are several power domains in which the operating (clock) frequency of

the processor is increased or decreased based on the amount of tasks in a given time. When the operating frequency

needs to be changed, it is expected that the corresponding buck converter responds to a command for changing its

output voltage to a new target value with a specific slew rate.

Whenever a new target value is written in the Mx_VOUT_H[7:0] bits through I2C while the corresponding buck is enabled,

the output voltage starts to change. The output voltage ramps up (or down) at a positive (or negative) slew rate set by

the corresponding Mx_RU_SR[2:0] (or Mx_RD_SR[2:0]) bits. When the Mx_FSREN bit is set, the corresponding buck

enters FPWM mode automatically (regardless of the Mx_FPWM bit) during the output voltage ramp-down (or soft-stop).

In FPWM mode, the buck can sink current from the COUTx to the PGNDx through the low-side MOSFET which allows

the VOUTx to track the negative rate set by the Mx_RD_SR[2:0] bits.

Table 10. Mx_FSREN Effect on Buck Behavior

OPERATING

MODE

Mx_FSREN

BUCK BEHAVIOR IN STEADY

STATE

BUCK BEHAVIOR DURING DYNAMIC VOLTAGE

SCALING

Skip or LP-Skip

Source Only

Source or Sink

FPWM

Source or Sink

Note: Buck outputs (VOUTx) with current sinking capability can follow the negative ramp rates set by the Mx_RD_SR[2:0]

or the Mx_SSTOP_SR[2:0].

If the negative inductor current reaches the INLIM (typ -3A), the low-side MOSFET is turned off immediately and the buck

initiates a new on-time (high-side MOSFET turn-on). Thus, the maximum slew rate during output-voltage ramp-down (or

soft-stop) is limited if an effective output capacitance is very high for the selected ramp-down (or soft-stop) slew rate. The

maximum output-voltage slew rate is calculated by following formula, dVC/dt = iC/C.

Output-Voltage Active Discharge

Each buck converter integrates a 100Ω active discharge resistor between the LXx and the PGNDx for discharging the

output capacitor when the buck output is disabled. For faster output-voltage discharge at the end of soft-stop, a 1Ω active

discharge function is added. Those two active discharge resistors are individually enabled by setting the Mx_ADIS100

and the Mx_ADIS1 bits, respectively. If both the Mx_ADIS100 and the Mx_ADIS1 are set to 1, the 1Ω active discharge is

first activated for 1ms right after soft-stop is completed, and the 100Ω active discharge is then enabled until the next time

the buck is enabled. In shutdown mode (CE = 0), the 100Ω active discharge of each buck phase is deactivated.

Note that the 1Ω active discharge function of the corresponding output must be disabled (Mx_ADIS1 = 0) to avoid

excessive power dissipation when the falling slew-rate control feature is disabled (Mx_FSREN = 0).

Bootstrap Refresh

When the buck is in drop-out operation or in skip (or LP-skip) mode under extremely light load condition, the low-side

MOSFET does not turn on for a long period of time. In this case, the buck controller occasionally turns on the low-side

MOSFET for about 100ns (typ) to charge a bootstrap circuit for driving the high-side MOSFET. The bootstrap-refresh

interval is set to 128μs by default. The bootstrap-refresh interval can be reduced to 10μs when the Mx_REFRESH bit is

set to 1. The bootstrap-refresh interval selection is shown in Table 11.

Table 11. Bootstrap-Refresh Interval Selection

Mx_REFRESH

REFRESH INTERVAL

128μs

10μs

The bootstrap refresh is also required when the buck converter starts switching. As a part of the startup procedure, the

MAX77542

16VIN/16A, Quad-Phase High-Efficiency Buck

Converter

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