MB9AF131KB datasheet(70/89 Pages) SPANSION

70 / 89 page

D a t a S h e e t

June 9, 2015, MB9A130LB_DS706-00066-2v0-E

CONFIDENTIAL

12-bit A/D Converter

 Electrical characteristics for the A/D converter

(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

INL

± 3.0

LSB

AVCC ≥ 2.7 V

± 5.0

LSB

AVCC < 2.7 V

Differential Nonlinearity

DNL

± 1.9

LSB

AVCC ≥ 2.7 V

± 2.9

LSB

AVCC < 2.7 V

Zero transition voltage

VZT

ANxx

± 20

Full-scale transition voltage

VFST

ANxx

AVRH ± 20

Conversion time*

1.0

μs

AVCC ≥ 2.7 V

4.0

AVCC < 2.7 V

Sampling time*

0.3

μs

AVCC ≥ 2.7 V

1.2

AVCC < 2.7 V

Compare clock cycle*

tCCK

1000

AVCC ≥ 2.7 V

200

AVCC < 2.7 V

Period of operation enable

state transitions

tSTT

μs

Analog input capacity

CAIN

Analog input resistor

RAIN

0.9

kΩ

AVCC ≥ 4.5 V

1.6

2.7 V ≤ AVCC < 4.5 V

4.0

AVCC < 2.7 V

Interchannel disparity

LSB

Analog port input leak

current

ANxx

0.3

μA

Analog input voltage

ANxx

AVSS

AVRH

Reference voltage

AVRH

2.7

AVCC

AVCC ≥ 2.7 V

AVCC

AVCC < 2.7 V

*1: The conversion time is the value of sampling time (tS) + compare time (tC).

The condition of the minimum conversion time is the following.

AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs

AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs

Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).

For setting*

4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family

Peripheral Manual Analog Macro Part.

The register settings of the A/D Converter are reflected in the operation according to the APB bus clock

timing.

For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.

The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle.

*2: A necessary sampling time changes by external impedance.

Ensure to set the sampling time to satisfy (Equation 1).

*3: The compare time (tC) is the value of (Equation 2).

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