MB9AF131KB datasheet(5/89 Pages) SPANSION

5 / 89 page

D a t a S h e e t

MB9A130LB_DS706-00066-2v0-E, June 9, 2015

CONFIDENTIAL

 Features

 32-bit ARM Cortex-M3 Core

 Processor version: r2p1

 Up to 20MHz Operation Frequency

 Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and

32 channels' peripheral interrupts and 8 priority levels

 24-bit System timer (Sys Tick): System timer for OS task management

 On-chip Memories

[Flash memory]

 Up to 128 Kbytes

 Read cycle: 0 wait-cycle

 Security function for code protection

[SRAM]

This series contains 8 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core.

 SRAM1: 8 Kbytes

 Multi-function Serial Interface (Max 8channels)

Operation mode is selectable from the followings for each channel.

 UART

 CSIO

 I

[UART]

 Full-duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Various error detection functions available (parity errors, framing errors, and overrun errors)

[CSIO]

 Full-duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detection function available

2C]

Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported

 A/D Converter (Max 8channels)

[12-bit A/D Converter]

 Successive Approximation type

 Conversion time: Min. 1.0 μs

 Priority conversion available (priority at 2 levels)

 Scanning conversion mode

 Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:

4 steps)

MB9AF131KB Datasheet(PDF) 5 Page - SPANSION

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