STM32MP251C datasheet(39/241 Pages) STMICROELECTRONICS

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3.51

Tamper and backup registers (TAMP)

The 128 x 32-bit backup registers are retained in all low-power modes, and in VBAT mode. They can be used to

store sensitive data as their content is protected by a tamper detection circuit. 16 tamper pins (eight input and

eight outputs), and 14 internal tampers are available for anti-tamper detection.

The eight external tamper pins can be configured for edge detection, edge and level, level detection with filtering,

or up to eight active tamper which increases the security level by auto-checking that tamper pins are not

externally opened or shorted.

•

128 backup registers (TAMP_BKPxR) implemented in the RTC domain that remains powered-on by VBAT

when the VDD power is switched off

•

8 external tamper detection events:

–

Each external event can be configured to be active or passive.

–

External passive tampers with configurable filter and internal pull-up

•

14 internal tamper events

•

Any tamper detection can generate an RTC timestamp event.

•

Any tamper detection erases backup registers.

•

TrustZone support:

–

Tamper secure or non-secure configuration

–

Backup registers configuration in three configurable-size areas:

◦

1 read/write secure area

◦

1 write secure/read non-secure area

◦

1 read/write non-secure area

•

Monotonic counter

3.52

Inter-integrated circuit interface (I2C1/2/3/4/5/6/7/8)

STM32MP25xC/F devices embed eight I2C interfaces, that handle communications between the device and the

serial I2C bus. Each I2C interface controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and master modes, multimaster capability

–

Standard-mode (Sm), with a bitrate up to 100 Kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 Kbit/s

–

Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Optional clock stretching

•

System management bus (SMBus) specification rev 2.0 compatibility:

–

Hardware PEC (packet error checking) generation and verification with ACK control

–

Address resolution protocol (ARP) support

–

SMBus alert

•

Power system management protocol (PMBus) specification rev 1.1 compatibility

•

Independent clock: a choice of independent clock sources that allows the I2C communication speed to be

independent from the PCLK reprogramming

•

Wake-up from Stop mode on address match

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

3.53

Improved inter-integrated circuit (I3C1/2/3/4)

STM32MP25xC/F devices embed four I3C interfaces, that handle communication between the device and others

that are all connected on an I3C bus, like sensors and host processors.

STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F

Functional overview

DS14284 - Rev 3

page 39/241

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