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STM32MP251C Datasheet(PDF) 13 Page - STMicroelectronics |
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STM32MP251C Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 241 page  3 Functional overview 3.1 Dual-core Arm Cortex-A35 subsystem (CA35SS) Note: Features may be limited or absent in some devices or packages (see Section 2 for details). 3.1.1 Features • Armv8-A architecture • AArch32 for full backward compatibility with Armv7 • AArch64 for 64-bit support and new architectural features • 32-Kbyte L1 instruction cache for each CPU • 32-Kbyte L1 data cache for each CPU • 512-Kbyte level2 cache • Arm A64 + A32 + Thumb-2 instruction set • Arm TrustZone security technology • Arm NEON advanced SIMD • DSP and SIMD extensions • VFPv4 floating-point • Hardware virtualization support • Performance monitoring Uuit (PMU) • Program trace macrocell (PTM) that supports instruction trace only • Integrated generic interrupt controller (GIC) with 384 shared peripheral interrupts • Integrated generic timer (CNT) Note: The cryptographic extension is not supported. 3.1.2 Overview The Cortex-A35 processor uses a highly-efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency. 3.1.2.1 Thumb-2 technology Delivers the peak performance of traditional Arm code, while also providing up to a 30 % reduction in memory requirement for instructions storage. 3.1.2.2 TrustZone technology Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry partners. 3.1.2.3 PMU The PMU provides six performance monitors that can be configured to gather statistics on the operation of each core and the memory system. The information can be used for debug and code profiling. 3.1.2.4 NEON and FPU Advanced SIMD is a media and signal processing architecture that adds instructions primarily for audio, video, 3 ‑D graphics, image, and speech processing. The floating-point architecture provides support for single-precision and double-precision floating-point operations. All scalar floating-point instructions are available in the A64 instruction set. All VFP instructions are available in A32 and T32 instruction sets. The same advanced SIMD instructions are available in both A32 and T32 instruction sets. The A64 instruction set offers additional advanced SIMD instructions, including double-precision floating-point vector operations. STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F Functional overview DS14284 - Rev 3 page 13/241 |
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