STM32MP251C datasheet(7/241 Pages) STMICROELECTRONICS

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two Octo-SPI flash memory interface , with on-the-fly content decryption

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two camera interfaces for CMOS sensors, one with basic ISP, demosaicing and parallel or MIPI CSI

interface

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an LCD-TFT display interface

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a MIPI DSI display interface (optional)

•

an LVDS display interface (optional)

A comprehensive set of power-saving mode allows the design of low-power applications.

STM32MP25xC/F devices are proposed in various packages up to 436 balls with 0.5 mm to 0.8 mm pitch. The set

of included peripherals can change with the selected device.

These features make STM32MP25xC/F devices suitable for a wide range of consumer, industrial, white goods

and medical applications.

Figure 1 shows the general block diagram of STM32MP25xC/F devices.

Table 1. STM32MP25xC/F features and peripheral counts

Features

STM32MP25xC/F

Package

TFBGA361 (16×16 pitch 0.8 mm),

VFBGA361 (10×10 pitch 0.5 mm),

VFBGA424 (14×14 pitch 0.5 mm),

TFBGA436 (18×18 pitch 0.8 mm)(1)

CPU processor

Up to dual-core Cortex-A35 FPU Neon

TrustZone, up to 1500 MHz(1)

ROM

128 Kbytes (only for Cortex-A35)

GPU

Optional VeriSilicon GC8000UL up to

900 MHz(1)

NPU

MCU processor

Cortex-M33 FPU TrustZone

Caches size

16-Kbyte data cache

16-Kbyte instruction cache

Frequency

400 MHz

SmartRun processor

Cortex-M0+

Frequency

16 MHz

Video

Decoder (VDEC)

H264/VP8 up to 1080p60

JPEG 500 Mpixel/s(1)

Encoder (VENC)

Video RAM

Up to 128 Kbytes(1)

Embedded SRAM (808 Kbytes)

CPU system

Up to 384 Kbytes(1)

MCU system

256 Kbytes (128 Kbytes tamper protected)

MCU retention

128 Kbytes

SmartRun domain

32 Kbytes

Backup

8 Kbytes (tamper protected)

SDRAM

DDR3L

1066 MHz

Up to 4 Gbytes(1)

DDR4

1200 MHz

LPDDR4

1200 MHz

Backup registers

512 bytes (128 × 32-bits, tamper protected)

Timers

Advanced

16 bits

General purpose

16 bits

32 bits

STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F

Description

DS14284 - Rev 3

page 7/241

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