STM32MP251C datasheet(21/241 Pages) STMICROELECTRONICS

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VDDCPU monitoring

Monitors VDDCPU power supply, and compares it to a configurable threshold. A tamper event, an interrupt,

or a wake-up can be generated when VDDCPU is below or above the threshold.

•

VDDGPU monitoring

Monitors VDDGPU power supply and compares it to a configurable threshold. An interrupt or a wake-up can

be generated when VDDGPU is below or above the threshold. A GPU reset is also generated if VDDGPU is

below the threshold (VDDGPURDY = 0).

•

Peripheral voltage monitoring

Monitors independently VDDIO2, VDDIO3, VDDIO4, VDDIO1, VDD33UCPD, VDD33USB and VDDA18ADC power

supplies with fixed thresholds. An interrupt or a wake-up can be generated when supplies are below or

above the thresholds.

3.10

Low-power strategy

Several low-power modes are available to save power when the Cortex-A35 and/or the Cortex-M33 do not need

to execute code (when waiting for an external event). It is up to the user to select the mode that gives the best

compromise between low-power consumption, short startup time, and available wake-up sources.

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Slowing down system clocks (see RCC section in the reference manual)

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Controlling individual peripheral clocks (see RCC section in the reference manual)

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Low-power modes:

–

CSleep (CPU clock stopped)

–

CStop (CPU subsystem clock stopped)

–

D1 DStop1 (CPU subsystem clock stopped, normal mode signaled to external regulator)

–

D1 DStandby (domain power down and wake-up via reset)

–

Stop1, LP-Stop1, and LPLV-Stop1 (system clock stalled, normal or low-power mode signaled to

external regulator supplying the VDDCPU and the VDDCORE)

–

Stop2, LP-Stop2, and LPLV-Stop2 (system clock stalled, powered down mode signaled to external

regulator supplying the VDDCPU, and normal or low-power mode signaled to external regulator

supplying the VDDCORE)

–

Standby1 (system powered down and D3 domain in autonomous mode running with local clocks)

–

Standby2 (system powered down, D3 domain also in power down)

3.11

Resource isolation framework (RIF)

The RIF is a comprehensive set of hardware blocks designed to enforce and manage the isolation of STM32

hardware resources like memory and peripherals.

Within a defined hardware execution compartment (eight are available), privileged, unprivileged, secure, and non-

secure application softwares can assign their own embedded memory buffers, external memory regions, and

peripherals thanks to the RIF hardware.

The RIF architectural framework extends to FMC, SYSCFG, IPCC, HSEM, DMA, RTC, TAMP, RCC, PWR, EXTI,

or GPIO.

3.12

Reset and clock controller (RCC)

Note:

Features may be limited or absent in some devices or packages (see Section 2 for details).

The RCC manages the generation of all clocks, as well as the clock gating and the control of system and

peripheral resets. It provides a high flexibility in the choice of clock sources, and allows application of clock ratios

to improve the power consumption. In addition, on some communication peripherals that are capable to work with

two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can

be changed without modifying the peripheral activity rate.

STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F

Functional overview

DS14284 - Rev 3

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