STM32MP251C datasheet(22/241 Pages) STMICROELECTRONICS

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3.12.1

Features

•

RIF aware

•

Reset part:

–

Generation of local and system reset

–

Bidirectional pad reset (NRST) to reset of external devices, or to reset the device

–

Output pad reset (NRSTC1MS) to reset of external mass-storage devices used by the Cortex-A35

•

Clock generation part:

–

Generation and distribution of clocks for the complete system

–

5 separate PLLs (excluding external Cortex-A35, DDRCTRL, and GPU ones):

◦

Integer or fractional mode

◦

Spread-spectrum function to reduce the amount of EMI peaks

◦

Possibility to change on-the-fly the fractional ratios of the PLLs

–

Smart clock gating for reduction of power dissipation

–

2 external oscillators:

◦

HSE that supports a wide range of crystals: 16 to 48 MHz

◦

LSE for 32.768 kHz crystals

–

3 Internal oscillators:

◦

HSI that runs around 64 MHz

◦

MSI that runs around 16 MHz or 4 MHz

◦

LSI that runs around 32 kHz

–

Buffered clock outputs for external devices

•

Two independent interrupt interfaces (one dedicated to Cortex-A35, and one dedicated to Cortex-M33)

•

Two independent failure events (HSE and LSE)

•

Two independent events to wake up processors (one dedicated to Cortex-A35 and one dedicated to

Cortex-M33)

3.12.2

Clock management

The RCC provides a high flexibility to the application in the choice of the clock generators:

•

from HSI, high-speed internal oscillator (~ 64 MHz)

•

from HSE, high-speed external oscillator (16 to 48 MHz)

•

from LSE; low-speed external oscillator (32 kHz)

•

from LSI, low-speed internal oscillator (~ 32 kHz)

•

from MSI, low-power internal oscillator (~ 4 MHz or ~ 16 MHz)

The RCC offers a good flexibility for the application to select the appropriate clock for CPUs and peripherals.

More especially for peripherals that need a specific clock like SPI(I2S), SAI, and SDMMC.

Each clock source can be switched on or off independently in order to optimize the power consumption.

There are mainly three clock paths:

•

Cortex-A35 bus matrix

•

Cortex-M33 and its bus matrix

•

peripheral kernel clocks

The Cortex-A35, the GPU, and DDRCTRL clocking are derived locally because of high frequency use. The RCC

manages only source clocks for their related local PLLs.

3.12.3

Reset sources

There are several sources able to generate a reset:

•

supply monitors (VDD, VDDCORE, VDDCPU , VDDGPU or VSW) lower than expected values

•

independent watchdogs timeout

•

D1 domain exit from DStandby state

•

exit from Standby mode

•

external signals driving the NRST pin

STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F

Functional overview

DS14284 - Rev 3

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