STM32MP251C datasheet(35/241 Pages) STMICROELECTRONICS

35 / 241 page

3.44

Cryptographic processor (CRYP1/2)

The devices embed two cryptographic processor that can be used both to encrypt and decrypt data using the

DES, triple-DES, or AES algorithms. The implementation if fully compliant with the following standards:

•

DES and TDES are defined by FIPS (PUB 46-3, Oct 1999), and by the American National Standards

Institute (ANSI X9.52)

•

AES is defined by FIPS (FIPS PUB 197, Nov 2001)

Multiple key sizes and chaining modes are supported:

•

DES/TDES chaining modes ECB and CBC, supporting standard 56-bit keys with 8-bit parity per key

•

AES chaining modes ECB, CBC, CTR, GCM, GMAC, CCM for key sizes of 128, 192, or 256 bits

The CRYP in AES mode supports key sharing from SAES co-processor. It is a 32-bit AHB peripheral with DMA

support for incoming and outgoing data.

The CRYP also includes input and output FIFOs (each 8 words deep) for better performance.

3.45

Secure AES (SAES)

The SAES encrypts or decrypts data, using an algorithm and implementation fully compliant with the AES

standard. It implements embedded protection against differential power analysis (DPA) and related side-channel

attacks.

The SAES supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits, as

well as special modes such as hardware secret key encryption/decryption (wrapped-key mode) and key sharing

with faster CRYP peripheral (shared-key mode).

The SAES can load directly two hardware master keys that are not directly accessible by any software. These

keys can be used to encrypt random keys that are usable only on this device, and are not directly accessible by

software.

The SAES supports DMA single transfers for incoming and outgoing data (two DMA channels required). It is

connected by hardware to the RNG and to the CRYP1/2.

The SAES is an AMBA AHB slave peripheral.

3.46

Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically those related to RSA,

Diffie-Hellmann, or ECC (elliptic curve cryptography) over GF(p) (Galois fields). To achieve high performance at a

reasonable cost, these operations are executed in the Montgomery domain.

For a given operation, all needed computations are performed within the accelerator: no further hardware/

software elaboration is needed to process inputs or outputs.

3.47

Boot and security and OTP control (BSEC)

The BSEC is used to control an OTP (one-time programmable) fuse box, used for embedded non-volatile storage

for device configuration and security parameters.

Embedded non-volatile secrets are stored in the BSEC upper area that is only accessible while BSEC is operating

in a closed state. In open state those non-volatile secrets are permanently hidden.

The BSEC use is reserved to trusted domain CPU, and boot CPU following a BSEC reset (cold/warm or hot).

3.48

Timers and watchdogs

The devices include three advanced-control timers, twelve general-purpose timers, two basic timers, five low-

power timers, seven watchdogs, two SysTick timers in Cortex-M33 , one SysTick timer in Cortex-M0+, and four

system timers in each Cortex-A35.

All timer counters can be frozen in debug mode.

The table below compares features of the different timers.

STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F

Functional overview

DS14284 - Rev 3

page 35/241

STM32MP251C Datasheet(PDF) 35 Page - STMicroelectronics

STM32MP251C Datasheet(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL