IS25LP256D-RGLA3 datasheet(77/174 Pages) ISSI

Part #	IS25LP256D-RGLA3

Description	SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

PDF	174 Pages

Scroll/Zoom	100%

Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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77 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

Figure 8.26 Quad Input Page Program operation (32h/38h [EXTADD=1] or 34h/3Eh, 4-byte address)

4-byte Address

Instruction = 32h/38h/34h/3Eh

CE #

SCK

High Impedance

...

Mode 3

Mode 0

IO0

IO1

Data In 2

IO2

IO3

...

Data In 1

...

8.12 ERASE OPERATION

The memory array of the device is organized into uniform 4 Kbyte sectors or 32/64 Kbyte uniform blocks (a block

consists of eight/sixteen adjacent sectors respectively).

Before a byte is reprogrammed, the sector or block that contains the byte must be era

sed (erasing sets bits to “1”).

In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase (BER),

and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting the

data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole

memory array of a device. A sector erase, block erase, or chip erase operation can be executed prior to any

programming operation.

IS25LP256D-RGLA3 Datasheet(PDF) 77 Page - Integrated Silicon Solution, Inc