IS25LP256D-RGLA3 datasheet(37/174 Pages) ISSI

37 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

Persistent Protection Mode

The Persistent Protection Mode sets the PPB Lock bit to

“1” during power up or Hardware Reset so that the PPB

bits are unprotected by a device Hardware Reset. Software Reset does not affect the PPB Lock bit. The WRPLB

command can clear the PPB Lock bit to

“0” to protect the PPB. There is no command to set the PPB Lock bit

therefore the PPB Lock bit will remain at

“0” until the next power up or Hardware Reset.

Password Protection Mode

The Password Protection Mode allows an even higher level of security than the Persistent Protection Mode by

requiring a 64-bit password for unlocking the device PPB Lock bit. In addition to this password requirement, after

power up or Hardware Reset, the PPB Lock bit is cleared to

“0” to maintain the password mode of operation.

Successful execution of the Unlock Password command by entering the entire password sets the PPB Lock bit to

“1”, allowing for sector/block PPBs modifications.

Notes:

1. The password

is all “1”s when shipped from Factory. It is located in its own memory space and is accessible through the use

of the Program Password and Read Password commands.

2. Once the Password is programmed and verified, the Password Protection Mode Lock Bit (ASPR[2]=0) in ASP Register must

be programmed in order to prevent reading or modifying the password. After the Password Protection Mode Lock Bit is

programmed, all further Program and Read commands to the password region are disabled and these commands are

ignored so that there is no means to verify what the password is. Password verification is only allowed before selecting the

Password Protection Mode.

3. The Program Password Command is only capable of programming

“0”s. Programming a “1” after a cell is programmed as a

“0” results in the cell left as a “0” with no programming error.

4. All 64-bit password combinations are valid as a password.

5. The Protection Mode Lock Bits in ASP Register are not erasable because they are OTP.

6. The exact password must be entered in order for the unlocking function to occur. If the password provided by Unlock

Password command does not match the hidden internal password, the unlock operation fails in the same manner as a

programming operation on a protected sector/block. The P_ERR and PROT_E are set to 1 and the PPB Lock bit remains

cleared to 0. In this case it is a failure to change the state of the PPB Lock bit because it is still protected by the lack of a

valid password.

7. The Unlock Password com

mand cannot be accepted any faster than once every 100μs ± 20μs. This makes it take an

unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly

match a password. The Read Status Register command or the Read Extended Read Register may be used to read the WIP

bit to determine when the device has completed the Unlock Password command or is ready to accept a new password

command. When a valid password is provided the Unlock Password command

does not insert the 100μs delay before

returning the WIP bit to zero.

8. If the password is lost after selecting the Password Protection Mode, there is no way to set the PPB Lock bit.

IS25LP256D-RGLA3 Datasheet(PDF) 37 Page - Integrated Silicon Solution, Inc

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