IS25LP256D-RGLA3 datasheet(56/174 Pages) ISSI

56 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

8.6 FAST READ DUAL I/O OPERATION (FRDIO, BBh or 4FRDIO, BCh)

The Fast Read Dual I/O (FRDIO, 4FRDIO) instruction allows the address bits to be input two bits at a time. This

may allow for code to be executed directly from the SPI in some applications.

 BBh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 BBh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 BCh is followed by a 4-byte address (A31-A0)

The FRDIO/4FRDIO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 4 clocks), transmitted via the IO1 and IO0 lines, with each pair of bits latched-in during the

rising edge of SCK. The address MSB is input on IO1, the next bit on IO0, and this shift pattern continues to

alternate between the two lines. Depending on the usage of AX read operation mode, a mode byte may be located

after address input.

The first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a maximum

frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1, while simultaneously the second

bit is output on IO0. Figures 8.7 and 8.8 illustrates the timing sequence.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDIO/4FRDIO instruction. The

FRDIO/4FRDIO instruction is terminated by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8

bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO/4FRDIO execution.

M7 to M4 are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah),

it enables the AX read operation and subsequent FRDIO/4FRDIO execution skips command code. It saves cycles

as described in Figures 8.9 and 8.10.

When the code is different from AXh (where X is don’t care), the device exits

the AX read operation. After finishing the read operation, device becomes ready to receive a new command. SPI

or QPI mode configuration retains the prior setting. Mode bit must be applied during dummy cycles. Number of

dummy cycles in Table 6.11 includes number of mode bit cycles. If dummy cycles are configured as 4 cycles, data

output will start right after mode bit is applied.

If the FRDIO/4FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not affect the current cycle.

IS25LP256D-RGLA3 Datasheet(PDF) 56 Page - Integrated Silicon Solution, Inc