IS25LP256D-RGLA3 datasheet(59/174 Pages) ISSI

59 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

Figure 8.9 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=0], 3-byte address)

CE #

SCK

3-byte Address

...

Mode 3

Mode 0

...

IO0

IO1

4 Dummy Cycles

Data Out 1

Mode Bits

...

Data Out 2

...

Notes:

If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

Figure 8.10 Fast Read Dual I/O AX Read Sequence (BBh [EXTADD=1] or BCh, 4-byte address)

CE #

SCK

4-byte Address

...

Mode 3

Mode 0

...

IO0

IO1

4 Dummy Cycles

Data Out 1

Mode Bits

...

Data Out 2

...

Notes:

1. If the mode bits=A

Xh (where X is don’t care), it will keep executing the AX read mode (without command). When the

mode bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

IS25LP256D-RGLA3 Datasheet(PDF) 59 Page - Integrated Silicon Solution, Inc

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