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IS25LP256D-RGLA3 Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc

Part # IS25LP256D-RGLA3
Description  SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  174 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP256D-RGLA3 Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc

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IS25LP256D
IS25WP256D
Integrated Silicon Solution, Inc.- www.issi.com
7
Rev A6
04/15/2019
1. PIN CONFIGURATION
Top View, Balls Facing Down
NC
NC
NC
NC
F1
F2
F3
F4
NC
RESET#(NC)
NC
SCK
GND
VCC
NC
CE#
NC
WP#(IO2)
NC
SO(IO1)
SI(IO0)
HOLD# or
RESET# (IO3)
NC
NC
NC
NC
NC
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
A1
(3)
(1,2)
24-ball TFBGA, 4x6 Ball Array (Package:G)
NC
NC
RESET#/(NC)
NC
SCK
GND
VCC
NC
CE#
NC
WP#(IO2)
NC
SO(IO1)
SI(IO0)
HOLD# or
RESET# (IO3)
NC
NC
NC
NC
NC
NC
NC
NC
Top View, Balls Facing Down
NC
24-ball TFBGA, 5x5 Ball Array (Package:H)
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
A5
B5
C5
D5
E5
NC
(3)
(1,2)
NC
Notes:
1.
The pin can be configured as Hold# or Reset# by setting P7 bit of the Read Register. Pin default is Hold#.
2.
Dedicated RESET# pin is available in devices with a dedicated part number, in these devices Pin 1 (16-pin
SOIC) or ball D4 (24-ball TFBGA) are set to Hold# regardless of P7 setting of the Read Register.
16-pin SOIC 300mil
(1)
(3)
(1,2)
6
3
CE#
Vcc
SCK
SI (IO0
)
7
8
5
4
1
2
GND
WP# (IO2)
SO (IO1)
HOLD# or
RESET# (IO3)
8-contact WSON 8x6mm
12
10
11
9
13
15
14
5
7
6
8
4
2
3
16
1
Vcc
HOLD# (IO3)
HOLD# or RESET# (IO3)
SCK
CE#
WP# (IO2)
GND
NC
NC
NC
NC
NC
SI (IO0)
SO (IO1)
NC
NC
RESET#/NC



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