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IS25LP256D-RGLA3 Datasheet(PDF) 20 Page - Integrated Silicon Solution, Inc

Part # IS25LP256D-RGLA3
Description  SERIAL FLASH MEMORY WITH 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE
PDF  174 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LP256D-RGLA3 Datasheet(HTML) 20 Page - Integrated Silicon Solution, Inc

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IS25LP256D
IS25WP256D
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev A6
04/15/2019
6.3 READ REGISTER AND EXTENDED REGISTER
Read Register format and bit definitions are described below. Read Register and Extended Read Register consist
of a pair of rewritable non-volatile register and volatile register, respectively. During power up sequence, volatile
register will be loaded with the value of non-volatile value.
6.3.1 READ REGISTER
Table 6.7 and Table 6.8 define all bits that control features in SPI/QPI modes. HOLD#/RESET# pin selection (P7)
bit is used
to select HOLD# pin or RESET# pin in SPI mode when QE=“0” for the device with HOLD#/RESET#.
When QE=1 or in QPI mode, P7 bit setting will be ignored since the pin becomes IO3.
For 16-pin SOIC or 24-ball TFBGA with dedicated RESET# device (Dedicated RESET# Disable bit in Functional
Register is “0”), HOLD# will be selected regardless of P7 bit setting when QE=“0” in SPI mode.
The SET READ PARAMETERS Operations (SRPNV: 65h, SRPV: C0h or 63h) are used to set all the Read Register
bits, and can thereby define HOLD#/RESET# pin (or ball) selection, dummy cycles, and burst length with wrap
around. SRPNV is used to set the non-volatile register and SRPV is used to set the volatile register.
Table 6.7 Read Register Parameter Bit Table
P7
P6
P5
P4
P3
P2
P1
P0
HOLD#/
RESET#
Dummy
Cycles
Dummy
Cycles
Dummy
Cycles
Dummy
Cycles
Wrap
Enable
Burst
Length
Burst
Length
Default
0
0
0
0
0
0
0
0
Table 6.8 Read Register Bit Definition
Bit
Name
Definition
Read-
/Write
Type
P0
Burst Length
Burst Length
R/W
Non-Volatile
and Volatile
P1
Burst Length
Burst Length
R/W
Non-Volatile
and Volatile
P2
Burst Length
Set Enable
Burst Length Set Enable Bit:
"0" indicates disable (default)
"1" indicates enable
R/W
Non-Volatile
and Volatile
P3
Dummy Cycles
Number of Dummy Cycles:
Bits1 to Bit4 can be toggled to select the number of dummy cycles
(1 to 15 cycles)
R/W
Non-Volatile
and Volatile
P4
Dummy Cycles
R/W
Non-Volatile
and Volatile
P5
Dummy Cycles
R/W
Non-Volatile
and Volatile
P6
Dummy Cycles
R/W
Non-Volatile
and Volatile
P7
HOLD#/
RESET#
HOLD#/RESET# function selection Bit:
"0" indicates the HOLD# function is selected (default)
"1" indicates the RESET# function is selected
R/W
Non-Volatile
and Volatile
Table 6.9 Burst Length Data
P1
P0
8 bytes
0
0
16 bytes
0
1
32 bytes
1
0
64 bytes
1
1



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