IS25LP256D-RGLA3 datasheet(27/174 Pages) ISSI

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IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

6.6 ADVANCED SECTOR/BLOCK PROTECTION (ASP) RELATED REGISTER

6.6.1 ADVANCED SECTOR/BLOCK PROTECTION REGISTER (ASPR)

Related Commands: Read ASP (RDASP 2Bh) and Program ASP (PGASP 2Fh).

Advanced Sector/Block Protection (ASP) Register Bit (16 bits) definitions are described in Tables 6.19 and 6.20.

Table 6.19 Advanced Sector/Block Protection Register (ASPR) Bit Table

7 to 14

TBPARM

Reserve

PWDMLB

PSTMLB

Reserve

Default

Table 6.20 Advanced Sector/Block Protection Register (ASPR) Bit Definition

Bit

Name

Definition

Read-

/Write

Type

Reserved

PSTMLB

Persistent Protection Mode Lock Bit

“0” = Persistent Protection Mode permanently enabled.

“1” = Persistent Protection Mode not permanently enabled.

R/W

OTP

PWDMLB

Password Protection Mode Lock Bit

“0” = Password Protection Mode permanently enabled.

“1” = Password Protection Mode not permanently enabled.

R/W

OTP

3:14

Reserved

TBPARM

Configures Parameter Sectors location

“0” = 4KB physical sectors at top, (high address)

“1” = 4KB physical sectors at bottom (Low address)

R/W

OTP

The Advanced Sector/Block Protection Register (ASPR) is used to permanently configure the behavior of Advanced

Sector/Block Protection (ASP) features and parameter sectors location.

PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) bits: When shipped from the factory, all devices default ASP to the

Persistent Protection Mode, with all sectors unprotected, when power is applied. The device programmer or host

system must then choose which sector/block protection method to use. Programming either of the Protection Mode

Lock Bits locks the part permanently in the selected mode:

 ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.

 ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.

 ASPR[2:1] = 01 = Password Protection Mode permanently selected.

 ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure

and the program operation will abort. It will result in a programming error with P_ERR set to 1.

As a result, PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to zero.

ASPR programming rules:

 If the Password Protection Mode is chosen, the password must be programmed prior to setting the

corresponding bit.

 Once the Protection Mode is selected, the ASPR[2:1] bits are permanently protected from programming and no

further change to the ASPR[2:1] is allowed. Attempting to program ASPR[2:1] after selected will result in a

programming error with P_ERR set to 1. The programming time of the ASPR is the same as the typical page

programming time. The system can determine the status of the ASPR programming operation by reading the

WIP bit in the Status Register or Extended Read Register.

 TBPARM bit can be programmed even after ASPR[2:1] bits are programmed while the FREEZE bit in the PPB

Lock Register is “0”.

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