IS25LP256D-RGLA3 datasheet(26/174 Pages) ISSI

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IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

6.5 BANK ADDRESS REGISTER

Related Commands: Read Volatile Bank Address Register (RDBR 16h/C8h), Write Volatile Bank Address Register

(WRBRV 17h/C5h), Write Non-Volatile Bank Address Register (WRBRNV 18h), Enter 4-byte Address Mode (EN4B

B7h), and Exit 4-byte Address Mode (EX4B 29h).

Bank Address Register Bit (8 bits) definitions are described in Table 6.17 and Table 6.18.

Table 6.17 Bank Address Register Bit Table

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

EXTADD

Reserved

BA24

Default

Table 6.18 Bank Address Register Bit Definition

Bit

Name

Definition

Read-

/Write

Type

BA0

BA24

Enables 128Mb segment selection in 3-byte addressing

"0" indicates lower 128Mb segment is selected.

"1" indicates upper 128Mb segment is selected.

R/W

Non-Volatile

and Volatile

BA1

Reserved

BA2

Reserved

BA3

Reserved

BA4

Reserved

BA5

Reserved

BA6

Reserved

BA7

EXTADD

3-byte or 4-byte addressing selection Bit:

"0" indicates 3-byte addressing.

"1" indicates 4-byte addressing.

R/W

Non-Volatile

and Volatile

BA24: The Bank Address Register supplies additional high order bits of the main flash array byte boundary address

for legacy commands that supply only the low order 24 bits of address. The Bank Address is used as the high bits

of address (above A23) for all 3-byte address commands when EXTADD=0. The Bank Address is not used when

EXTADD = 1 and traditional 3-byte address commands are instead required to provide all four bytes of address.

EXTADD: Extended Address (EXTADD) controls the address field size for legacy SPI commands. When shipped

from factory, it is cleared

to “0” for 3 bytes (24 bits) of address. When set to “1”, the legacy commands will require

4 bytes (32 bits) for the address field.

IS25LP256D-RGLA3 Datasheet(PDF) 26 Page - Integrated Silicon Solution, Inc

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