IS25LP256D-RGLA3 datasheet(17/174 Pages) ISSI

17 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

Table 6.3 Instructions requiring WREN instruction ahead

Instructions must be preceded by the WREN instruction

Name

Hex Code

Operation

02h

Serial Input Page Program (3-byte or 4-byte Address)

4PP

12h

Serial Input Page Program (4-byte Address)

PPQ

32h/38h

Quad Input Page Program (3-byte or 4-byte Address)

4PPQ

34h/3Eh

Quad Input Page Program (4-byte Address)

SER

D7h/20h

Sector Erase 4KB (3-byte or 4-byte Address)

4SER

21h

Sector Erase 4KB (4-byte Address)

BER32 (32KB)

52h

Block Erase 32KB (3-byte or 4-byte Address)

4BER32 (32KB)

5Ch

Block Erase 32KB (4-byte Address)

BER64 (64KB)

D8h

Block Erase 64KB (3-byte or 4-byte Address)

4BER64 (64KB)

DCh

Block Erase 64KB (4-byte Address)

CER

C7h/60h

Chip Erase

WRSR

01h

Write Status Register

WRFR

42h

Write Function Register

SRPNV

65h

Set Read Parameters (Non-Volatile)

SERPNV

85h

Set Extended Read Parameters (Non-Volatile)

IRER

64h

Erase Information Row

IRP

62h

Program Information Row

WRABR

15h

Write AutoBoot Register

WRBRNV

18h

Write Non-Volatile Bank Address Register

PGPPB

FDh

Write PPB (3-byte or 4-byte Address)

4PGPPB

E3h

Write PPB (4-byte Address)

ERPPB

E4h

Erase PPB

PGASP

2Fh

Program ASP

WRPLB

A6h

Write PPB Lock Bit

SFRZ

91h

Set FREEZE bit

PGPWD

E8h

Program Password

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of

the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a defined

combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any program or

erase operation to that area will be inhibited.

Note: A Chip Erase (CER) instruction will be ignored unless

all the Block Protection Bits are “0”s.

SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)

signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-

protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register (SRWD, QE,

BP3, BP2, BP1, BP0) become read-

only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and

WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the QE

bit is set to “0”, the pin WP# and HOLD#/RESET# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins

are enabled.

WARNING: The QE bit must be set

to “0” if WP# or HOLD#/RESET# pin (or ball) is tied directly to the power supply.

IS25LP256D-RGLA3 Datasheet(PDF) 17 Page - Integrated Silicon Solution, Inc

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