IS25LP256D-RGLA3 datasheet(63/174 Pages) ISSI

63 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

8.8 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh or 4FRQO 6Ch)

The FRQO/4FRQO instruction is used to read memory data on four output pins each at up to a 166 MHz clock.

A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad Output instruction.

 6Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 6Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 6Ch is followed by a 4-byte address (A31-A0)

The FRQO/4FRQO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising

edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with

each group of four bits shifted out at a maximum frequency f CT, during the falling edge of SCK. The first

bit (MSB) is output on IO3, while simultaneously the second bit is output on IO2, the third bit is output on

IO1, etc.

The first byte addressed can be at any memory location. The address is automatically incremented afte r

each byte of data is shifted out. When the highest address is reached, the address counter will roll over

to the 000000h address, allowing the entire memory to be read with a single FRQO/ 4FRQO instruction.

FRQO/4FRQO instruction is terminated by driving CE# high (VIH).

If a FRQO/4FRQO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not have any effects on the current cycle.

IS25LP256D-RGLA3 Datasheet(PDF) 63 Page - Integrated Silicon Solution, Inc