IS25LP256D-RGLA3 datasheet(60/174 Pages) ISSI

60 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

8.7 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh or 4FRDO, 3Ch)

The FRDO/4FRDO instruction is used to read memory data on two output pins each at up to a 166MHz clock.

 3Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

 3Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

 3Ch is followed by a 4-byte address (A31-A0)

The FRDO/4FRDO instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 8 clocks), transmitted via the IO0 line, with each bit latched-in during the rising edge of SCK.

Then the first data byte addressed is shifted out on the IO1 and IO0 lines, with each pair of bits shifted out at a

maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO1. Simultaneously, the

second bit is output on IO0.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. W hen the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDO/4FRDO instruction. The instruction

FRDO/4FRDO is terminated by driving CE# high (VIH).

If the FRDO/4FRDO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the

instruction is ignored and will not have any effects on the current cycle.

IS25LP256D-RGLA3 Datasheet(PDF) 60 Page - Integrated Silicon Solution, Inc