IS25LP256D-RGLA3 datasheet(97/174 Pages) ISSI

97 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

Read with “8/16/32/64-Byte Wrap Around”

The device is capable of burst read with wrap around in both SPI and QPI mode. The size of burst length is

configurable by using P0, P1, and P2 bits in Read Register. P2 bit (Wrap enable) enables the burst mode feature.

P0 and P1 define the size of burst. Burst lengths of 8, 16, 32, and 64 bytes are supported. By default, address

increases by one up through the entire array. By setting the burst length, the data being accessed can be limited

to the length of burst boundary within a 256 byte page. The first output will be the data at the initial address which

is specified in the instruction. Following data will come out from the next address within the burst boundary. Once

the address reaches the end of boundary, it will automatically move to the first address of the boundary. CE# high

will terminate the command.

For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from address

00h and continue to 01h,..,07h, 00h, 01h… until CE# terminates the operation. If burst length of 8 and initial address

being applied is FEh(254d), following byte output will be from address FEh and continue to FFh, F8h, F9h, FAh,

FBh, FCh, FDh, and repeat from FEh until CE# terminates the operation.

The commands, “SRPV (65h) or SRPNV (C0h or 63h)”, are used to configure the burst length. If the following data

input is one of “00h”,”01h”,”02h”, and ”03h”, the device will be in default operation mode. It will be continuous burst

read of the whole array. If the following data input is o

ne of “04h”,”05h”,”06h”, and ”07h”, the device will set the

burst length as 8,16,32 and 64, respectively.

To exit the burst mode, another “C0h or 63h” command is necessary to set P2 to 0. Otherwise, the burst mode will

be retained until either power down

or reset operation. To change burst length, another “C0h or 63h” command

should be executed to set P0 and P1 (Detailed information in Table 6.9 Burst Length Data). All read commands

will operate in burst mode once the Read Register is set to enable burst mode.

Refer to Figure 8.59 and Figure 8.60 for instruction sequence.

IS25LP256D-RGLA3 Datasheet(PDF) 97 Page - Integrated Silicon Solution, Inc