IS25LP256D-RGLA3 datasheet(10/174 Pages) ISSI

10 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

For the device with dedicated RESET#

SYMBOL

TYPE

DESCRIPTION

CE#

INPUT

Same as the description in previous page

SI (IO0),

SO (IO1)

INPUT/

OUTPUT

Same as the description in previous page

WP# (IO2)

INPUT/

OUTPUT

Same as the description in previous page

HOLD# (IO3)

INPUT/

OUTPUT

HOLD#/Serial Data IO (IO3):

When the QE bit of Status Register is set to “1”, HOLD#

pin is not available since it becomes IO3. When QE=0 the pin acts as HOLD#

regardless of the P7 bit of Read Register.

The HOLD# pin allows the device to be paused while it is selected. It pauses serial

communication by the master device without resetting the serial sequence. The

HOLD# pin is active low. When HOLD# is in a low state and CE# is low, the SO pin

will be at high impedance. Device operation can resume when HOLD# pin is brought

to a high state.

RESET#

INPUT

RESET#: This pin is available only for dedicated parts (Call Factory for 24-ball

TFBGA 6x8mm packages).

The RESET# pin is a hardware RESET signal. When RESET# is driven HIGH, the

memory is in the normal operating mode. When RESET# is driven LOW, the memory

enters reset mode and output is High-Z. If RESET# is driven LOW while an internal

WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

SCK

INPUT

Same as the description in previous page

Vcc

POWER

Same as the description in previous page

GND

GROUND

Same as the description in previous page

Unused

Same as the description in previous page

IS25LP256D-RGLA3 Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc

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