PIIX datasheet(70/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.5.3.1.

ICW1—Initialization Command Word 1 Register

I/O Address:

INT CNTRL-1—020h; INT CNTRL-2—0A0h

Default Value:

All bits undefined

Attribute:

Write Only

A write to Initialization Command Word 1 starts the interrupt controller initialization sequence. Addresses

020h and 0A0h are referred to as the base addresses of CNTRL-1 and CNTRL-2, respectively. An I/O write to

the CNTRL-1 or CNTRL-2 base address with bit 4 equal to 1 is interpreted as ICW1. For PIIX-based ISA

systems, three I/O writes to "base address + 1" must follow the ICW1. The first write to "base address + 1"

performs ICW2, the second write performs ICW3, and the third write performs ICW4.

ICW1 starts the initialization sequence during which the following automatically occur:

The Interrupt Mask register is cleared.

IRQ7 input is assigned priority 7.

The slave mode address is set to 7.

Special Mask Mode is cleared and Status Read is set to IRR.

If IC4 was set to 0, then all functions selected by ICW4 are set to 0. However, ICW4 must be

programmed in the PIIX/PIIX3 implementation of this interrupt controller, and IC4 must be set to a 1.

Bit

Description

7:5

ICW/OCW select. These bits should be 000 when programming the PIIX.

ICW/OCW select. Bit 4 must be a 1 to select ICW1. After the fixed initialization sequence to

ICW1, ICW2, ICW3, and ICW4, the controller base address is used to write to OCW2 and

OCW3. Bit 4 is a 0 on writes to these registers. A 1 on this bit at any time will force the

interrupt controller to interpret the write as an ICW1. The controller will then expect to see

ICW2, ICW3, and ICW4.

Edge/Level Bank Select (LTIM). This bit is disabled. Its function is replaced by the

Edge/Level Triggered Control (ELCR) Registers.

ADI. Ignored for the PIIX.

Single or Cascade (SNGL). This bit must be programmed to a 0.

ICW4 Write Required (IC4). This bit must be set to a 1.

2.5.3.2.

ICW2—Initialization Command Word 2 Register

I/O Address:

INT CNTRL-1—021h; INT CNTRL-2—0A1h

Default Value:

All bits undefined

Attribute:

Write Only

ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector

address.

Bit

Description

7:3

Interrupt Vector Base Address. Bits [7:3] define the base address in the interrupt vector

table for the interrupt routines associated with each interrupt request level input.

2:0

Interrupt Request Level. Must be programmed to all 0s.

PIIX Datasheet(PDF) 70 Page - Intel Corporation

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