PIIX datasheet(23/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

ISA Compatible Registers

The ISA-Compatible registers (e.g., DMA registers, timer/counter registers, X-Bus registers, and NMI

registers) are accessed through normal I/O space. Except for the DMA registers, the PIIX/PIIX3 positively

decodes accesses to the ISA-Compatible registers. The PIIX/PIIX3 subtractively decodes accesses to all I/O

space registers contained within the ISA-Compatible DMA function. This permits another device in the

system to implement the compatible DMA function.

PCI master accesses to the ISA-Compatible registers can be 8, 16, 24, or 32 bits. However, the PIIX/PIIX3

only responds to the least significant byte. On writes the other bytes are not loaded and on reads the other

bytes have invalid data. The PIIX/PIIX3 responds as an 8-bit ISA I/O slave when accessed by an ISA master.

See the PCI Local Bus IDE section for accesses to the IDE register blocks located in the IDE device

In general, accesses from CPU or PCI masters to the internal PIIX/PIIX3 registers are not broadcast to the

ISA Bus. Exceptions to this are read/write accesses to 70h and F0h and write accesses to 80h, 84–86h, 88h,

8C–8Eh, 90h, 94–96h, 98h, and 9C–9Eh. These accesses are broadcast to the ISA Bus. Note that aliasing of

the 90–9Fh to 80–8Fh can be enabled/disabled via the ISA Controller Recovery Timer Register.

Power Management Registers

There are two power management registers located in normal I/O space. These registers are accessed (by

PCI Bus masters) with 8-bit accesses. The other power management registers are located in PCI

configuration space for function 0.

PCI Bus Master IDE Registers

The PCI Bus master IDE function uses 16 bytes located in normal I/O space, allocated via the BMIBA

32-bit quantities.

Universal Serial Bus Registers

A set of USB registers provide control and status information for the Host Controller and two USB ports

(Table 7). This block of registers is I/O mapped into PCI I/O space and control variouos operations of the

USB Host Controller. The registers are relocateable via the USBBASE Register which is located in function 0

PCI configuration space.

Table 2. PCI Configuration Registers—Function 0 (PCI to ISA Bridge)

Configuration

Offset

Mnemonic

Access

00–01h

VID

Vendor Identification

02–03h

DID

Device Identification

04–05h

PCICMD

PCI Command

R/W

06–07h

PCISTS

PCI Device Status

R/WC

08h

RID

Revision Identification

−0Bh

CLASSC

Class Code

0C–0Dh

—

Reserved

—

0Eh

HEDT

Header Type

PIIX Datasheet(PDF) 23 Page - Intel Corporation

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