PIIX datasheet(63/122 Pages) INTEL

63 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

2.5.1.4.

Mask Register—Write Single Mask Bit

I/O Address:

Channels 0-3—0Ah; Channels 4-7—0D4h

Default Value:

Bits[1:0]=undefined; Bit 2=1; Bits[7:3]=0 (CPURST or a Master Clear)

Attribute:

Write Only

A channel's mask bit is automatically set when the Current Byte/Word Count Register reaches terminal

count (unless the channel is programmed for autoinitialization). Setting the entire register disables all

DMA requests until a clear mask register instruction allows them to occur. This instruction format is

similar to the format used with the DMA Request Register. Masking DMA channel 4 (DMA controller 2,

channel 0) also masks DMA channels [3:0].

Bit

Description

7:3

Reserved. Must be 0.

Channel Mask Select. 1=Disable DREQ for the selected channel. 0=Enable DREQ for the

selected channel.

1:0

DMA Channel Select. Bits [1:0] select the DMA Channel Mode Register for bit 2.

Bits[1:0]

Channel

Channel 0 (4)

Channel 1 (5)

Channel 2 (6)

Channel 3 (7)

2.5.1.5.

Mask Register—Write All Mask Bits

I/O Address:

Channels 0-3—0Fh; Channels 4-7—0DEh

Default Value:

Bit[3:0]=1; Bit[7:4]=0 (CPURST or Master Clear)

Attribute:

Read/Write

A channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches

terminal count (unless the channel is programmed for autoinitialization). Setting bits [3:0] to 1 disables

all DMA requests until a clear mask register instruction enables the requests. Note that, masking DMA

channel 4 (DMA controller 2, channel 0), masks DMA channels [3:0]. Also Note that, Masking DMA

controller 2 with a write to port 0DEh also masks DREQ assertions from DMA controller 1.

Bit

Description

7:4

Reserved. Must be 0.

3:0

Channel Mask Bits. 1=Disable the corresponding DREQ(s); 0=Enable the corresponding

DREQ(s).

Bit

Channel

0 (4)

1 (5)

2 (6)

3 (7)

PIIX Datasheet(PDF) 63 Page - Intel Corporation

PIIX Datasheet(HTML) 63 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL