PIIX datasheet(39/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

PIIX: ISA Clock Divisor Status

RO. This bit reports the strapping option on the SYSCLK

signal. 1=clock divisor of 3 (PCICLK=25 MHz). 0=Clock divisor of 4 (PCICLK=33 MHz). Note

that, for PCICLK=30 MHz, a clock divisor of 4 must be selected and produces a SYSCLK of

7.5 MHz.

PIIX3: ISA Clock Divisor

R/W. This bit controls the frequency of the SYSCLK signal.

1=clock divisor of 3 (PCICLK=25 MHz). 0=Clock divisor of 4 (PCICLK=33 MHz). Note that, for

PCICLK=30 MHz, a clock divisor of 4 must be selected and produces a SYSCLK of 7.5 MHz.

The default value of this bit is determined by the strapping option on the SYSCLK signal.

2.2.13.

MBIRQ[1:0]—MOTHERBOARD DEVICE IRQ ROUTE CONTROL REGISTERS (Function 0)

Address Offset :

70h—MBIRQ0 (PIIX and PIIX3)

71h—MBIRQ1 (PIIX only)

Default Value:

80h

Attribute:

R/W

These registers control the routing of motherboard device interrupts (MIRQ[1:0]) to the internal IRQ inputs of

the interrupt controller. Each MIRQx# can be independently routed to any one of 11 interrupts.

Note that, when an MIRQ line and a PIRQ# line are steered to the same ISA interrupt, the device connected

to the MIRQ line must be set for active high, level interrupts. In this case, the ISA interrupt will be masked. Bit

6 of that motherboard device IRQ Route Control Register must be programmed to a 0.

Bit

Description

Interrupt Routing Enable. 0=Enable routing; 1=Disable routing.

MIRQx/IRQx Sharing Enable. 0=Disable sharing; 1=Enable sharing. When sharing is

disabled and bit 7 of this register is 0, the interrupt specified by bits [3:0] is masked. Interrupt

sharing should only be enabled when the device connected to the MIRQ line and the device

connected to the ISA IRQ line both produce active high, level interrupts.

PIIX: Reserved

PIIX3: IRQ0 Enable, 1=Enable (IRQ0 Output), 0 = Disable (default, MIRQ0 input). When

enabled the MIRQ0/IRQ0 pin functions as the IRQ0 output and the IDE Interrupt Status flag in

Bus Master IDE Status Register is set by the IRQ15 input signal. When disabled the

MIRQ0/IRQ0 pin functions as the MIRQ0 input and the IDE Interrupt Status flag in the Bus

Master IDE Status Register is set by the MIRQ0 input signal.

Reserved. Read as zero.

3:0

Interrupt Routing. When bit 7=0, this field selects the routing of the MBIRQx to one of the

interrupt controller interrupt inputs.

Bits[3:0]

IRQ Routing

Bits[3:0]

IRQ Routing

Bits[3:0]

IRQ Routing

0000

Reserved

0110

IRQ6

1011

IRQ11

0001

Reserved

0111

IRQ7

1100

IRQ12

0010

Reserved

1000

Reserved

1101

Reserved

0011

IRQ3

1001

IRQ9

1110

IRQ14

0100

IRQ4

1010

IRQ10

1111

IRQ15

0101

IRQ5

PIIX Datasheet(PDF) 39 Page - Intel Corporation

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