PIIX datasheet(98/122 Pages) INTEL

98 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

3.5.2.1.

Back-To-Back PIO IDE Transactions

IDE data port transaction latency consists of startup latency, cycle latency, and shutdown latency. Cycle

latency consists of the I/O strobe assertion length and recovery time. Recovery time is provided so that

transactions may occur back-to-back on the IDE interface (without incurring startup and shutdown latency)

without violating minimum cycle periods for the IDE interface.

Startup latency is incurred when a PCI master cycle targeting the IDE data port is decoded and the DA[2:0]

and CSxx# lines are not set up. Startup latency provides the setup time for the DA[2:0] and CSxx# lines with

respect to the read and write strobes (DIOR# and DIOW#).

Shutdown latency is incurred after outstanding scheduled IDE data port transactions (either a non-empty

write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can

proceed. It provides hold time on the DA[2:0] and CSxx# lines with respect to the read and write strobes

(DIOR# and DIOW#).

Cycle latency is the latency incurred by each individual 16-bit IDE data port transfer, and consists of

command strobe width and recovery time. The command strobe assertion width is selected by the IDETIM

and may be set to 1, 2, 3, or 4 PCI clocks.

For the PIIX3, the master drive (drive 1) and slave drive (drive 0) can be programmed to different command

strobe assertion widths and recovery times via the IDETIM and SIDETIM Registers.

If IORDY is asserted when the initial sample point is reached, no wait states are added. If IORDY is negated

when the initial sample point is reached, additional wait states are added. Since the rising edge of IORDY

must be synchronized, at least two additional PCI clocks are added.

NOTE

Bit 2 (16-bit I/O recovery enable) of the ISA Controller Recovery Timer Register does not add wait

states to IDE data port read accesses when any of the fast timing modes are enabled.

3.5.2.2.

IORDY Masking

The IORDY signal can be forced asserted on a drive by drive basis via the IDETIM Register.

3.5.2.3.

PIO 32 Bit IDE Data Port Mode

If the 32-bit IDE data port mode is enabled (via bit 4 and 0 of the IDETIM Register), 32-bit accesses to the

IDE data port address (default 01F0h primary, etc.) result in two back to back 16-bit transactions to IDEThe

32-bit data port feature is enabled for all timings, not just enhanced timing.

3.5.3.

BUS MASTER FUNCTION

The PIIX/PIIX3 can act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master channels

are provided—one channel for each IDE connector (primary and secondary). By performing the IDE data

transfer as a PCI Bus master, the PIIX/PIIX3 off-loads the CPU and improves system performance in

multitasking environments.

Physical Region Descriptor Format

The physical memory region to be transferred is described by a Physical Region Descriptor (PRD). The PRDs

are stored in a table in memory. The data transfer proceeds until all regions described by the PRDs in the

table have been transferred. Note that the bus master IDE does not support memory for regions or PRDs on

ISA.

PIIX Datasheet(PDF) 98 Page - Intel Corporation

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