PIIX datasheet(32/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

Bus Master Enable (BME). (Not Implemented) The PIIX/PIIX3 does not support disabling

its bus master capability. This bit is hardwired to 1.

Memory Access Enable (MAE). (Not Implemented) The PIIX/PIIX3 does not support

disabling access to main memory. This bit is hardwired to 1.

I/O Space Access Enable (IOSE). The PIIX/PIIX3 does not support disabling its response to

PCI I/O cycles. This bit is hardwired to 1.

2.2.4.

PCISTS—PCI DEVICE STATUS REGISTER (Function 0)

Address Offset:

06–07h

Default Value:

0200h

Attribute:

Read/Write Clear

The PCISTS Register reports the occurrence of a PCI master-abort by the PIIX/PIIX3 or a PCI target-abort

when the PIIX/PIIX3 is a master. The register also indicates the PIIX/PIIX3 DEVSEL# signal timing.

Bit

Description

Detected Parity Error (PERR). (Not Implemented) Read as 0.

PIIX: Signaled SERR# Status (SERRS). (Not Implemented) Read as 0.

PIIX3: Signaled SERR# Status (SERRS)—R/WC. When the PIIX3 asserts the SERR#

signal, this bit is set to 1. Software sets this bit to a 0 by writing a 1 to it

Master-Abort Status (MA)—R/WC. When the PIIX, as a master (for the ISA bridge function),

generates a master-abort, MA is set to a 1. Software sets MA to 0 by writing a 1 to this bit

location.

Received Target-Abort Status (RTA)—R/WC. When the PIIX/PIIX3 is a master on the PCI

Bus (for the ISA bridge function) and receives a target-abort, this bit is set to a 1. Software

sets RTA to 0 by writing a 1 to this bit location.

Signaled Target-Abort Status (STA)—R/WC. This bit is set when the PIIX/PIIX3 ISA bridge

function is targeted with a transaction that the PIIX/PIIX3 terminates with a target abort.

Software sets STA to 0 by writing a 1 to this bit location.

10:9

DEVSEL# Timing Status (DEVT)—RO. The PIIX/PIIX3 always generates DEVSEL# with

medium timing for ISA functions. Thus, DEVT=01. This DEVSEL# timing does not include

Configuration cycles.

PERR# Response. (Not Implemented) Read as 0.

Fast Back to Back—RO. This bit indicates to the PCI Master that PIIX/PIIX3 as a target is

capable of accepting fast back-to-back transactions.

6:0

Reserved. Read as 0s.

PIIX Datasheet(PDF) 32 Page - Intel Corporation

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