PIIX datasheet(60/122 Pages) INTEL

60 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

A20Gate Pass-through Enable (A20PTEN)

R/W. 1=Enable A20GATE pass-through

sequence. 0=Disable (default). When enabled, the logic will pass-through the following

A20GATE command sequence:

Cycle

Address

Data

Write

64h

D1h

( 1 or more) (Starts the Sequence)

Write

60h

xxh

Read

64h

N/A

( 0 or more)

Write

64h

FFh

( Standard End of A20GATE Pass-through Sequence)

Any deviation in the above sequence causes the host controller to immediately exit the

sequence and return to standard operation, performing an I/O trap and generating an SMI# if

appropriate enable bits are set.

When enabled, SMI# is not generated during the sequence, even if the various enable bits are

set. Note that during a pass-through sequence, the above status bits are not set for the I/O

accesses that are part of the sequence.

Trap/SMI ON IRQ Enable (USBSMIEN)

R/W. 1=Enable SMI# generation on USB IRQ.

0=Disable (default).

Trap/SMI On 64h Write Enable (64WEN)

R/W. 1=Enable I/O Trap and SMI# generation on

port 64h write.

0=Disable (default).

Trap/SMI On 64h Read Enable (64REN)

R/W. 1=Enable I/O Trap and SMI# generation on

port 64h read.

0=Disable (default).

Trap/SMI On 60h Write Enable (60WEN)

R/W. 1=Enable I/O Trap and SMI# generation on

port 60h write.

0=Disable (default).

Trap/SMI On 60h Read Enable (60REN)

R/W. 1 = Enable I/O Trap and SMI# generation on

port 60h read.

0=Disable (default).

PIIX Datasheet(PDF) 60 Page - Intel Corporation

PIIX Datasheet(HTML) 60 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL