PIIX datasheet(35/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

Bit

Description

15:9

PIIX3: Reserved.

PIIX3: APIC Chip Select. When enabled (bit 8=1), APICCS# is asserted for PCI memory

accesses to the programmable IOAPIC region. This cycle is forwarded to the ISA bus. The

default IOAPIC addresses are memory FEC0_0000h and FEC0_0010h. These can be

relocated via the APIC Base Address Relocation Register. When disabled (bit 8=0), the PCI

cycle is ignored by PIIX3 and APICCS# and XOE# are not generated. Note that APICCS# is

not generated for ISA-originated cycles. This bit also controls the function of two shared signals

on the PIIX3 as shown below:

Shared Signal Name

Bit 8=0

Bit 8=1

TESTIN#/APICREQ#

TESTIN#

APICREQ#

PCIRST#/APICACK#

PCIRST#

APICACK#

Extended BIOS Enable. When bit 7=1 (enabled), PCI master accesses to locations

FFF80000–FFFDFFFFh are forwarded to ISA and result in the generation of BIOSCS# and

XOE#. When forwarding the additional 384-Kbyte region at the top of 4 Gbytes, the PIIX/PIIX3

allows the PCI address A[23:20] to propagate to the ISA LA[23:20] lines as all 1's, aliasing this

384-Kbyte region to the top of the 16-Mbyte space. To avoid contention, ISA addin memory

must not be present in this region (00F80000–00FDFFFFh). When bit 7=0, the PIIX/PIIX3 does

not generate BIOSCS# or XOE#.

Lower BIOS Enable. When bit 6=1 (enabled), PCI master, or ISA master accesses to the

lower 64-Kbyte BIOS block (E0000–EFFFFh) at the top of 1 Mbyte, or the aliases at the top of

4 Gbyte (FFFE0000–FFFEFFFFh) result in the generation of BIOSCS# and XOE#. When

forwarding the region at the top of 4 Gbytes to the ISA Bus, the ISA LA[23:20] lines are all 1's,

aliasing this region to the top of the 16-Mbyte space. To avoid contention, ISA addin memory

must not be present in this region (00F80000–00FDFFFFh). When bit 6=0, the PIIX/PIIX3 does

not generate BIOSCS# or XOE# during these accesses and does not forward the accesses to

ISA.

Coprocessor Error function Enable. 1=Enable; the FERR# input, when asserted, triggers

IRQ13 (internal). FERR# is also used to gate the IGNNE# output.

IRQ12/M Mouse Function Enable. 1=Mouse function; 0=Standard IRQ12 interrupt function.

Reserved.

BIOSCS# Write Protect Enable. 1=Enable (BIOSCS# is asserted for BIOS memory read and

write cycles in decoded BIOS region); 0=Disable (BIOSCS# is only asserted for BIOS read

cycles).

Keyboard Controller Address Location Enable. 1=Enable KBCS# and XOE# for address

locations 60h and 64h. 0=Disable KBCS#/XOE# for accesses to these locations.

RTC Address Location Enable. 1=Enable RTCCS#/RTCALE and XOE# for accesses to

address locations 70–77h. 0=Disable RTCCS#/RTCALE and XOE# for these accesses.

PIIX Datasheet(PDF) 35 Page - Intel Corporation

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