PIIX datasheet(65/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.5.1.8.

DMA Base And Current Byte/Word Count Registers (Compatible Segment)

I/O Address:

DMA Channel 0—001h

DMA Channel 4—0C2h

DMA Channel 1—003h

DMA Channel 5—0C6h

DMA Channel 2—005h

DMA Channel 6—0CAh

DMA Channel 3—007h

DMA Channel 7—0CEh

Default Value:

XXXXh (CPURST or Master Clear)

Attribute:

Read/Write

This register determines the number of transfers to be performed. The actual number of transfers is one

more than the number programmed in the Current Byte/Word Count Register When the value in the

TC occurs. If it is not autoinitialized, this register has a count of FFFFh after TC.

For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be transferred.

This applies to DMA channels 0-3. For transfers to/from a 16-bit I/O, with shifted address, the

Byte/Word count indicates the number of 16-bit words to be transferred. This applies to DMA channels

5-7.

Bit

Description

15:0

Base and Current Byte/ Word Count. These bits represent the 16 byte/word count bits used

when counting down a DMA transfer.

2.5.1.9.

DMA Memory Low Page Registers

I/O Address:

DMA Channel 0—087h

DMA Channel 5—08Bh

DMA Channel 1—083h

DMA Channel 6—089h

DMA Channel 2—081h

DMA Channel 7—08Ah

DMA Channel 3—082h

Default Value:

XXh (CPURST or Master Clear)

Attribute:

Read/Write

This register works in conjunction with the Current Address Register. After an autoinitialization, this

Bit

Description

7:0

DMA Low Page [23:16]. These bits represent address bits [23:16] of the 24-bit DMA address

PIIX Datasheet(PDF) 65 Page - Intel Corporation

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