PIIX datasheet(22/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.0.

The 82371FB PIIX internal registers are organized into five groups—PCI Configuration Registers (function 0),

PCI Configuration Registers (function 1), ISA-Compatible Registers, PCI Bus Master IDE Registers, and

System Power Management Registers. These registers are discussed in this section.

The PIIX3 internal registers contain the same register sets as the PIIX plus two additional register sets for the

Universal Serial Bus (USB) function—PCI Configuration Registers (function 2) and the USB I/O Registers.

Some of the PIIX/PIIX3 registers contain reserved bits. Software must deal correctly with fields that are

reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved

bits being any particular value. On writes, software must ensure that the values of reserved bit positions are

preserved. That is, the values of reserved bit positions must first be read, merged with the new values for

other bit positions and then written back.

In addition to reserved bits within a register, the PIIX/PIIX3 contains address locations in the PCI

configuration space that are marked "Reserved". The PIIX/PIIX3 responds to accesses to these address

locations by completing the host cycle. Software should not write to reserved PIIX/PIIX3 configuration

locations in the device-specific region (above address offset 3Fh).

During a hard reset, the PIIX/PIIX3 sets its internal registers to predetermined default states. The default

values are indicated in the individual register descriptions.

The following notation is used to describe register access attributes:

Read Only. If a register is read only, writes have no effect.

Write Only. If a register is write only, reads have no effect.

R/W

Read/Write. A register with this attribute can be read and written. Note that individual bits in some

read/write registers may be read only.

R/WC

Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1

clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

2.1.

Table 2, Table 3, and Table 4 show the I/O assignments for the PCI Configuration Registers (function 0, 1,

and 2). Table 5 shows the I/O assignments for the ISA Compatible Registers. Table 6 shows the I/O

assignments for the Bus Master IDE Interface registers. Table 7 shows the I/O assignments for the USB I/O

registers. PCI masters have access to all PIIX/PIIX3 internal registers. In addition, ISA masters have access

to some of the ISA-Compatible registers (see Table 5).

PCI Configuration Registers (functions 0, 1, and 2)

The 82371FB PIIX is a multi-function device on the PCI Bus implementing two functions—PCI-to-ISA Bridge

(function 0) and IDE Interface (function 1). These functions can be independently configured with two sets of

PCI configuration registers in compliance with the PCI Local Bus Specification, Revision 2.0. The two sets of

configuration registers are accessed by the CPU through a mechanism defined for multi-functional PCI

devices. The PIIX does not assert DEVSEL# for PCI configuration cycles that target functions 2 through 7.

The PIIX3 implements an additional PCI bus function

Universial Serial Bus Interface. The PIIX3 does not

assert DEVSEL# for PCI configuration cycles that target functions 3 through 7.

PIIX Datasheet(PDF) 22 Page - Intel Corporation

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