PIIX datasheet(40/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.14.

MBDMA[1:0]—MOTHERBOARD DEVICE DMA CONTROL REGISTERS (Function 0)

Address Offset :

76h—MBDMA0#; 77h—MBDMA1#

Default Value:

0Ch

Attribute:

R/W

For both the PIIX and PIIX3, these registers enable/disable a type F DMA transfer (3 SYSCLK) for a

particular DMA channel.

For the PIIX, these registers also control the routing of motherboard device DMA signals (MDRQ[1:0] and

MDAK[1:0]) to the DREQ and DACK# signals on the 8237 DMA controller unit.

Bit

Description

Type F and DMA Buffer Enable (FAST). 1=Enable for the channel selected by bits[2:0].

0=Disable for the channel selected by bits[2:0].

6:4

Reserved.

PIIX: Disable Motherboard Channel (DMC). When this bit 3=0, the MDRQ/MDAK# pair

associated with this channel is routed to the compatable ISA channel determined by the CHNL

field (bits[2:0]). When bit 3=1, the ISA DREQ/DACK# pair is used for that channel.

When a MDRQ/MDAK# pair is programmed for a given 8237 DMA channel and DMC=0 (bit 3),

the corresponding DREQ/DACK# pins are masked for that channel. When DMC=1, the

MDRQ/MDAK# signals are masked. If both motherboard DMAs are used, the motherboard

DMAs should be programmed to different compatible DMA channels. Programming both

motherboard DMAs to the same compatible DMA channel results in unpredictable device

operation.

PIIX3: Reserved.

2:0

PIIX: Type F and Motherboard DMA Channel Routing (CHNL). When DMC=0, this field

steers the corresponding MDRQ/MDAK# signals to a compatable ISA channel for a

motherboard peripheral (and if FAST=1, also enables type F transfers and the 4-byte DMA

buffer). When DMC=1 and FAST=1, this field enables type F transfers and the 4-byte DMA

buffer for an ISA peripheral on a given channel.

PIIX3: Type F DMA Channel Routing (CHNL). When FAST=1, this field enables type F

transfers and the 4-byte DMA buffer for an ISA peripheral on the selected channel.

Bits[2:0]

DMA channel

Bits[2:0]

DMA channel

000

100

default (disabled)

001

101

010

110

011

111

2.2.15.

PCSC—PROGRAMMABLE CHIP SELECT CONTROL REGISTER (Function 0)

Address Offset:

78–79h

Default Value:

0002h

Attribute:

Read/Write

This register controls the assertion of the PCS# programmable chip select signal. The PCS# signal is

asserted for subtractively decoded I/O cycles generated by PCI masters that fall in the range specified by this

4, 8 or 16 bytes. A split range is precluded. The upper sixteen address bits (AD[31:16]) must be zero for the

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