PIIX datasheet(82/122 Pages) INTEL

82 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

Table 9. Run/Stop, Debug Bit Interaction

SWDBG

(Bit 5)

Run/Stop

(Bit 0)

Operation

If executing a command, the Host Controller completes the command and

then stops. The 1.0 ms frame counter is reset and command list execution

resumes from start of frame using the frame list pointer selected by the

current value in the FRNUM register. (While Run/Stop=0, the FRNUM register

can be reprogrammed).

Execution of the command list resumes from Start Of Frame using the frame

list pointer selected by the current value in the FRNUM register. The Host

Controller remains running until the Run/Stop bit is cleared (by Software or

Hardware).

If executing a command, the Host Controller completes the command and

then stops and the 1.0 ms frame counter is frozen at its current value. All

status are preserved. The Host Controller begins execution of the command

list from where it left off when the Run/Stop bit is set.

Execution of the command list resumes from where the previous execution

stopped. The Run/Stop bit is set to 0 by the Host Controller when a TD is

being fetched. This causes the Host Controller to stop again after the

execution of the TD (single step). When the Host Controller has completed

execution, the HC Halted bit in the Status Register is set.

2.8.2.

USBSTS

USB Status Register

I/O Address:

Base + (02

−03h)

Default Value:

0000h

Attribute:

Read/Write Clear

size:

16 bits

This register indicates pending interrupts and various states of the Host Controller. The status resulting from

a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by

writing a 1 to it.

Bit

Description

15:6

Reserved.

HCHalted. The Host Controller sets this bit to 1 after it has stopped executing as a result of

the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (an

internal error).

Host Controller Process Error. The Host Controller sets this bit to 1 when it detects a fatal

error and indicates that the Host Controller suffered a consistency check failure while

processing a Transfer Descriptor. An example of a consistency check failure would be finding

an illegal PID field while processing the packet header portion of the Transfer Descriptor (TD)

data structure. When this error occurs, the Host Controller clears the Run/Stop bit in the

Command register to prevent further schedule execution. A hardware reset is generated to

the system.

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