06489

April 16, 2012

Rev: C

EN6360QI

©

Enpirion 2011 all rights reserved, E&OE

Enpirion Confidential

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Falling Edge Deglitch Delay After

Output Crossing 90% level.

213

µs

0.4

V

V

POK Internal pull-up

resistor

94

kΩ

Current Balance

∆

With 2 to 4 Converters in Parallel,

the Difference Between Nominal

and Actual Current Levels.

∆

+/-10

%

Accuracy

∆

(Note 4)

(Note 5 and Note 6)

-25

+25

%

ENABLE Logic High

1.2

V

ENABLE Logic Low

0

0.8

V

ENABLE Pin Current

VIN = 6.6V

50

µ

A

M/S Ternary Pin Logic

Low

Tie M/S Pin to GND

0

0.7

V

M/S Ternary Pin Logic

Float

M/S Pin is Open

1.1

1.4

V

M/S Ternary Pin Logic

Hi (Note 7)

Pull Up to VIN through an external

1.8

V

Ternary Pin Input

Current

Ω

Ω

117

88

µ

A

Binary Pin Logic Low

Threshold

ENABLE, S_IN

0.8

V

Binary Pin Logic High

Threshold

ENABLE, S_IN

1.8

V

S_OUT Low Level

0.4

V

S_OUT High Level

2.0

V

Note 3: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing

the 90% level, there is a 256 clock cycle (~213µs at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels

are nominal values. Expect these thresholds to vary by ±3%.

Note 4: Parameter not production tested but is guaranteed by design.

Note 7: M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to

VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on.