06489

April 16, 2012

Rev: C

EN6360QI

©

Enpirion 2011 all rights reserved, E&OE

Enpirion Confidential

PIN

NAME

FUNCTION

26-27,

62-63

NC(SW)

NO CONNECT: These pins are internally connected to the common switching node of the

internal MOSFETs. They must be soldered to PCB but not be electrically connected to any

external signal, ground, or voltage. Failure to follow this guideline may result in device damage.

28-34

PGND

Input and output power ground. Connect these pins to the ground electrode of the input and

output filter capacitors. Refer to VOUT, PVIN descriptions and Layout Recommendation for

more details.

35-43

PVIN

Input power supply. Connect to input power supply and place input filter capacitor(s) between

these pins and PGND pins 32 to 34.

46

VDDB

Internal regulated voltage used for the internal control circuitry. Decouple with an optional

0.1µF capacitor to BGND for improved efficiency. This pin may be left floating if board space is

limited.

47

BGND

Ground for VDDB. Refer to pin 46 description.

48

S_IN

Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will

accept the S_OUT signal from another EN6360QI for parallel operation. A low level on the M/S

pin will make this device a Master and the switching frequency will be phase locked to an

external clock. Leave this pin floating if it is not used.

49

S_OUT

Digital output. A low level on the M/S pin will make this EN6360QI a Master and the internal

switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of

another EN6360QI device for parallel operation. Leave this pin floating if it is not used.

50

POK

POK is a logic level high when VOUT is within -10% to +20% of the programmed output

with a nominal value of 120k .

51

ENABLE

Device enable pin. A high level or floating this pin enables the device while a low level disables

the device. A voltage ramp from another power converter may be applied for precision enable.

Refer to Power Up Sequencing

52

AVIN

Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)

at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is

sequencing.

53

AGND

The quiet ground for the control circuits. Connect to the ground plane with a via right next to the

pin.

54

M/S

Ternary (three states) input pin. Floating this pin disables parallel operation. A low level

resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional

55

VFB

This is the external feedback input pin. A resistor divider connects from the output to AGND.

regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB

floating.

56

EAOUT

Error amplifier output. Allows for customization of the control loop. May be left floating.

57

SS

A soft-start capacitor is connected between this pin and AGND. The value of the capacitor

controls the soft-start interval. Refer to Soft-Start in the Functional Description for more details.

58

VSENSE

This pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect

VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low.

60

FQADJ

Frequency adjust pin. This pin must have a resistor to AGND which sets the free running

frequency of the internal oscillator.

61

EN_PB

Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up

under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is

pulled high internally. Enable pre-bias feature is not available for parallel operations.

69

PGND

Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-

sinking purposes. Refer to Layout Recommendation section.