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NPIZ Datasheet(PDF) 5 Page - Enpirion, Inc.

Part # NPIZ
Description  8A Synchronous Highly Integrated DC-DC PowerSoC
PDF  24 Pages
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Manufacturer  ENPIRION [Enpirion, Inc.]
Direct Link  http://www.enpirion.com
Logo ENPIRION - Enpirion, Inc.

NPIZ Datasheet(HTML) 5 Page - Enpirion, Inc.

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06489
April 16, 2012
Rev: C
EN6360QI
©
Enpirion 2011 all rights reserved, E&OE
Enpirion Confidential
www.enpirion.com, Page 5
Electrical Characteristics
NOTE: VIN=6.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input
Voltage
VIN
2.5
6.6
V
VFB Pin Voltage
VVFB
Internal Voltage Reference at:
VIN = 5V, ILOAD = 0, TA = 25°C
0.594
0.600
0.606
V
VFB Pin Voltage
(Line, Load and
Temperature)
VVFB
2.5V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 8A
0.588
0.600
0.612
V
VFB Pin Input Leakage
Current
IVFB
VFB Pin Input Leakage Current
-0.2
0.2
µ
A
Shut-Down Supply
Current
IS
Power Supply Current with
ENABLE=0
1.5
mA
Under Voltage Lock-
out – VIN Rising
VUVLOR
Voltage Above Which UVLO is Not
Asserted
2.2
V
Under Voltage Lock-
out – VIN Falling
VUVLOF
Voltage Below Which UVLO is
Asserted
2.1
V
Drop Out Voltage
VDO
VINMIN – VOUT at Full Load
400
800
mV
Drop Out Resistance
RDO
Input to Output Resistance
50
100
m
Continuous Output
Current
IOUT_SRC
0
8
A
Over Current Trip
Level
IOCP
Sourcing Current
16
A
Switching Frequency
FSW
RFADJ = 4.42 kΩ, VIN = 5V
0.9
1.2
1.5
MHz
External SYNC Clock
Frequency Lock
Range
FPLL_LOCK
SYNC Clock Input Frequency
Range
0.9*Fsw
Fsw
1.1*Fsw
MHz
S_IN Clock Amplitude
– Low
VS_IN_LO
SYNC Clock Logic Low
0
0.8
V
S_IN Clock Amplitude
– High
VS_IN_HI
SYNC Clock Logic High
1.8
2.5
V
S_IN Clock Duty Cycle
(PLL)
DCS_INPLL
M/S Pin Float or Low
20
80
%
S_IN Clock Duty Cycle
(PWM)
DCS_INPWM
M/S Pin High
10
90
%
Pre-Bias Level
VPB
Allowable Pre-bias as a Fraction of
Programmed Output Voltage for
Monotonic start up. Minimum Pre-
bias Voltage = 300mV.
20
75
%
Non-Monotonicity
VPB_NM
Allowable Non-monotonicity Under
Pre-bias Startup
100
mV
VOUT Range for POK =
High
Range of Output Voltage as a
Fraction of Programmed Value
When POK is Asserted. (Note 3)
90
120
%



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