R8CSLASH29 datasheet(285/471 Pages) RENESAS

285 / 471 page

R8C/28 Group, R8C/29 Group

16. Clock Synchronous Serial Interface

Rev.2.10

Sep 26, 2008

Page 268 of 441

REJ09B0279-0210

16.2.5.3

Data Reception

Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data

Reception (Clock Synchronous Communication Mode).

During data reception, clock synchronous serial I/O with chip select operates as described below. When clock

synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and inputs

data. When clock synchronous serial I/O with chip select is set as a slave device, it inputs data synchronized

with the input clock.

When clock synchronous serial I/O with chip select is set as a master device, it outputs a receive clock and starts

receiving by performing dummy read of the SSRDR register.

After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and

receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI

interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is

automatically set to 0 (no data in the SSRDR register).

Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the

receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8

bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to

0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR

When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun

error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm

that the ORER bit is set to 0 before restarting receive.

Figure 16.16 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication

Mode).

Figure 16.15

Example of Clock Synchronous Serial I/O with Chip Select Operation for Data

Reception (Clock Synchronous Communication Mode)

SSCK

SSI

• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at

even edges), and CPOS bit = 0 (“H” when clock stops)

1 frame

RDRF bit in

SSSR register

RSSTP bit in

SSCRH register

Dummy read in

SSRDR register

Processing

by program

RXI interrupt request

generation

1 frame

RXI interrupt request

generation

Read data in SSRDR

Read data in

SSRDR register

Set RSSTP bit to 1

RXI interrupt request

generation

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